xref: /linux/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml (revision 83bd89291f5cc866f60d32c34e268896c7ba8a3d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/T2H / RZ/N2H ADC12
8
9maintainers:
10  - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
11
12description: |
13  A/D Converter block is a successive approximation analog-to-digital converter
14  with a 12-bit accuracy. Up to 16 analog input channels can be selected.
15  Conversions can be performed in single or continuous mode. Result of the ADC
16  is stored in a 16-bit data register corresponding to each channel.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - const: renesas,r9a09g087-adc # RZ/N2H
23          - const: renesas,r9a09g077-adc # RZ/T2H
24      - items:
25          - const: renesas,r9a09g077-adc # RZ/T2H
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    items:
32      - description: A/D scan end interrupt
33      - description: A/D scan end interrupt for Group B
34      - description: A/D scan end interrupt for Group C
35      - description: Window A compare match
36      - description: Window B compare match
37      - description: Compare match
38      - description: Compare mismatch
39
40  interrupt-names:
41    items:
42      - const: adi
43      - const: gbadi
44      - const: gcadi
45      - const: cmpai
46      - const: cmpbi
47      - const: wcmpm
48      - const: wcmpum
49
50  clocks:
51    items:
52      - description: Converter clock
53      - description: Peripheral clock
54
55  clock-names:
56    items:
57      - const: adclk
58      - const: pclk
59
60  power-domains:
61    maxItems: 1
62
63  '#address-cells':
64    const: 1
65
66  '#size-cells':
67    const: 0
68
69  "#io-channel-cells":
70    const: 1
71
72patternProperties:
73  "^channel@[0-9a-f]$":
74    $ref: adc.yaml
75    type: object
76    description: The external channels which are connected to the ADC.
77
78    properties:
79      reg:
80        description: The channel number.
81        maximum: 15
82
83    required:
84      - reg
85
86    additionalProperties: false
87
88required:
89  - compatible
90  - reg
91  - interrupts
92  - clocks
93  - clock-names
94  - power-domains
95
96additionalProperties: false
97
98examples:
99  - |
100    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102
103    adc@80008000 {
104      compatible = "renesas,r9a09g077-adc";
105      reg = <0x80008000 0x400>;
106      interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
107                   <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
108                   <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
109                   <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
110                   <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
111                   <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
112                   <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
113      interrupt-names = "adi", "gbadi", "gcadi",
114                        "cmpai", "cmpbi", "wcmpm", "wcmpum";
115      clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
116               <&cpg CPG_MOD 225>;
117      clock-names = "adclk", "pclk";
118      power-domains = <&cpg>;
119      #address-cells = <1>;
120      #size-cells = <0>;
121      #io-channel-cells = <1>;
122
123      channel@0 {
124        reg = <0x0>;
125      };
126      channel@1 {
127        reg = <0x1>;
128      };
129      channel@2 {
130        reg = <0x2>;
131      };
132      channel@3 {
133        reg = <0x3>;
134      };
135    };
136