xref: /linux/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml (revision cb4eb6771c0f8fd1c52a8f6fdec7762fb087380a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm's SPMI PMIC ADC5 Gen3
8
9maintainers:
10  - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
11
12description: |
13  SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read
14  voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal
15  monitoring function as the existing ADC_TM devices.
16
17  The interface is implemented on SDAM (Shared Direct Access Memory) peripherals
18  on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC
19  SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is
20  programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
21  All boards using a particular (SOC + master PMIC) combination will have the
22  same number of ADC SDAMs supported on that PMIC.
23
24properties:
25  compatible:
26    const: qcom,spmi-adc5-gen3
27
28  reg:
29    items:
30      - description: SDAM0 base address in the SPMI PMIC register map
31      - description: SDAM1 base address
32    minItems: 1
33
34  "#address-cells":
35    const: 1
36
37  "#size-cells":
38    const: 0
39
40  "#io-channel-cells":
41    const: 1
42
43  "#thermal-sensor-cells":
44    const: 1
45
46  interrupts:
47    items:
48      - description: SDAM0 end of conversion (EOC) interrupt
49      - description: SDAM1 EOC interrupt
50    minItems: 1
51
52patternProperties:
53  "^channel@[0-9a-f]+$":
54    type: object
55    unevaluatedProperties: false
56    $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml
57    description:
58      Represents the external channels which are connected to the ADC.
59
60    properties:
61      qcom,decimation:
62        enum: [ 85, 340, 1360 ]
63        default: 1360
64
65      qcom,hw-settle-time:
66        enum: [ 15, 100, 200, 300, 400, 500, 600, 700,
67                1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ]
68        default: 15
69
70      qcom,avg-samples:
71        enum: [ 1, 2, 4, 8, 16 ]
72        default: 1
73
74      qcom,adc-tm:
75        description:
76          ADC_TM is a threshold monitoring feature in HW which can be enabled
77          on any ADC channel, to trigger an IRQ for threshold violation. In
78          earlier ADC generations, it was implemented in a separate device
79          (documented in Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.)
80          In Gen3, this feature can be enabled in the same ADC device for any
81          channel and threshold monitoring and IRQ triggering are handled in FW
82          (PBS) instead of another dedicated HW block.
83          This property indicates ADC_TM monitoring is done on this channel.
84        type: boolean
85
86required:
87  - compatible
88  - reg
89  - "#address-cells"
90  - "#size-cells"
91  - "#io-channel-cells"
92  - interrupts
93
94additionalProperties: false
95
96examples:
97  - |
98    #include <dt-bindings/interrupt-controller/irq.h>
99
100    pmic {
101      #address-cells = <1>;
102      #size-cells = <0>;
103
104      adc@9000 {
105        compatible = "qcom,spmi-adc5-gen3";
106        reg = <0x9000>, <0x9100>;
107        interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
108                      <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
109        #address-cells = <1>;
110        #size-cells = <0>;
111        #io-channel-cells = <1>;
112        #thermal-sensor-cells = <1>;
113
114        /* PMK8550 Channel nodes */
115        channel@3 {
116          reg = <0x3>;
117          label = "pmk8550_die_temp";
118          qcom,pre-scaling = <1 1>;
119        };
120
121        channel@44 {
122          reg = <0x44>;
123          label = "pmk8550_xo_therm";
124          qcom,pre-scaling = <1 1>;
125          qcom,ratiometric;
126          qcom,hw-settle-time = <200>;
127          qcom,adc-tm;
128        };
129
130        /* PM8550 Channel nodes */
131        channel@103 {
132          reg = <0x103>;
133          label = "pm8550_die_temp";
134          qcom,pre-scaling = <1 1>;
135        };
136
137        /* PM8550B Channel nodes */
138        channel@78f {
139          reg = <0x78f>;
140          label = "pm8550b_vbat_sns_qbg";
141          qcom,pre-scaling = <1 3>;
142        };
143
144        /* PM8550VS_C Channel nodes */
145        channel@203 {
146          reg = <0x203>;
147          label = "pm8550vs_c_die_temp";
148          qcom,pre-scaling = <1 1>;
149        };
150      };
151    };
152