xref: /linux/Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP Successive Approximation ADC
8
9description:
10  The NXP SAR ADC provides fast and accurate analog-to-digital
11  conversion using the Successive Approximation Register (SAR) method.
12  It has 12-bit resolution with 8 input channels. Conversions can be
13  launched in software or using hardware triggers. It supports
14  continuous and one-shot modes with separate registers.
15
16maintainers:
17  - Daniel Lezcano <daniel.lezcano@kernel.org>
18
19properties:
20  compatible:
21    oneOf:
22      - const: nxp,s32g2-sar-adc
23      - items:
24          - const: nxp,s32g3-sar-adc
25          - const: nxp,s32g2-sar-adc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    maxItems: 1
35
36  dmas:
37    maxItems: 1
38
39  dma-names:
40    const: rx
41
42required:
43  - compatible
44  - reg
45  - interrupts
46  - clocks
47  - dmas
48  - dma-names
49
50additionalProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55
56    adc@401f8000 {
57        compatible = "nxp,s32g2-sar-adc";
58        reg = <0x401f8000 0x1000>;
59        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
60        clocks = <&clks 0x41>;
61        dmas = <&edma0 0 32>;
62        dma-names = "rx";
63    };
64