1*1ea5792aSRadu Sabau# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1ea5792aSRadu Sabau%YAML 1.2 3*1ea5792aSRadu Sabau--- 4*1ea5792aSRadu Sabau$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# 5*1ea5792aSRadu Sabau$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1ea5792aSRadu Sabau 7*1ea5792aSRadu Sabautitle: Analog Devices AD4691 Family Multichannel SAR ADCs 8*1ea5792aSRadu Sabau 9*1ea5792aSRadu Sabaumaintainers: 10*1ea5792aSRadu Sabau - Radu Sabau <radu.sabau@analog.com> 11*1ea5792aSRadu Sabau 12*1ea5792aSRadu Sabaudescription: | 13*1ea5792aSRadu Sabau The AD4691 family are high-speed, low-power, multichannel successive 14*1ea5792aSRadu Sabau approximation register (SAR) analog-to-digital converters (ADCs) with 15*1ea5792aSRadu Sabau an SPI-compatible serial interface. The ADC supports CNV Burst Mode, 16*1ea5792aSRadu Sabau where an external PWM drives the CNV pin, and Manual Mode, where CNV 17*1ea5792aSRadu Sabau is directly tied to the SPI chip-select. 18*1ea5792aSRadu Sabau 19*1ea5792aSRadu Sabau Datasheets: 20*1ea5792aSRadu Sabau * https://www.analog.com/en/products/ad4691.html 21*1ea5792aSRadu Sabau * https://www.analog.com/en/products/ad4692.html 22*1ea5792aSRadu Sabau * https://www.analog.com/en/products/ad4693.html 23*1ea5792aSRadu Sabau * https://www.analog.com/en/products/ad4694.html 24*1ea5792aSRadu Sabau 25*1ea5792aSRadu Sabau$ref: /schemas/spi/spi-peripheral-props.yaml# 26*1ea5792aSRadu Sabau 27*1ea5792aSRadu Sabauproperties: 28*1ea5792aSRadu Sabau compatible: 29*1ea5792aSRadu Sabau enum: 30*1ea5792aSRadu Sabau - adi,ad4691 31*1ea5792aSRadu Sabau - adi,ad4692 32*1ea5792aSRadu Sabau - adi,ad4693 33*1ea5792aSRadu Sabau - adi,ad4694 34*1ea5792aSRadu Sabau 35*1ea5792aSRadu Sabau reg: 36*1ea5792aSRadu Sabau maxItems: 1 37*1ea5792aSRadu Sabau 38*1ea5792aSRadu Sabau spi-max-frequency: 39*1ea5792aSRadu Sabau maximum: 40000000 40*1ea5792aSRadu Sabau 41*1ea5792aSRadu Sabau spi-cpol: true 42*1ea5792aSRadu Sabau spi-cpha: true 43*1ea5792aSRadu Sabau 44*1ea5792aSRadu Sabau avdd-supply: 45*1ea5792aSRadu Sabau description: Analog power supply (4.5V to 5.5V). 46*1ea5792aSRadu Sabau 47*1ea5792aSRadu Sabau vdd-supply: 48*1ea5792aSRadu Sabau description: 49*1ea5792aSRadu Sabau External 1.8V digital core supply. When present, the internal LDO is 50*1ea5792aSRadu Sabau disabled (LDO_EN = 0). Mutually exclusive with ldo-in-supply. 51*1ea5792aSRadu Sabau 52*1ea5792aSRadu Sabau ldo-in-supply: 53*1ea5792aSRadu Sabau description: 54*1ea5792aSRadu Sabau LDO input supply (2.4V to 5.5V). When present and vdd-supply is absent, 55*1ea5792aSRadu Sabau the internal LDO generates 1.8V VDD from this input (LDO_EN = 1). 56*1ea5792aSRadu Sabau Mutually exclusive with vdd-supply. 57*1ea5792aSRadu Sabau 58*1ea5792aSRadu Sabau vio-supply: 59*1ea5792aSRadu Sabau description: I/O voltage supply (1.71V to 1.89V or VDD). 60*1ea5792aSRadu Sabau 61*1ea5792aSRadu Sabau ref-supply: 62*1ea5792aSRadu Sabau description: External reference voltage supply (2.4V to 5.25V). 63*1ea5792aSRadu Sabau 64*1ea5792aSRadu Sabau refin-supply: 65*1ea5792aSRadu Sabau description: Internal reference buffer input supply. 66*1ea5792aSRadu Sabau 67*1ea5792aSRadu Sabau reset-gpios: 68*1ea5792aSRadu Sabau description: 69*1ea5792aSRadu Sabau GPIO line controlling the hardware reset pin (active-low). 70*1ea5792aSRadu Sabau maxItems: 1 71*1ea5792aSRadu Sabau 72*1ea5792aSRadu Sabau pwms: 73*1ea5792aSRadu Sabau description: 74*1ea5792aSRadu Sabau PWM connected to the CNV pin. When present, selects CNV Burst Mode where 75*1ea5792aSRadu Sabau the PWM drives the conversion rate. When absent, Manual Mode is used 76*1ea5792aSRadu Sabau (CNV tied to SPI CS). 77*1ea5792aSRadu Sabau maxItems: 1 78*1ea5792aSRadu Sabau 79*1ea5792aSRadu Sabau interrupts: 80*1ea5792aSRadu Sabau description: 81*1ea5792aSRadu Sabau Interrupt lines connected to the ADC GP pins. Each GP pin can be 82*1ea5792aSRadu Sabau physically wired to an interrupt-capable input on the SoC. 83*1ea5792aSRadu Sabau maxItems: 4 84*1ea5792aSRadu Sabau 85*1ea5792aSRadu Sabau interrupt-names: 86*1ea5792aSRadu Sabau description: Names of the interrupt lines, matching the GP pin names. 87*1ea5792aSRadu Sabau minItems: 1 88*1ea5792aSRadu Sabau maxItems: 4 89*1ea5792aSRadu Sabau items: 90*1ea5792aSRadu Sabau enum: 91*1ea5792aSRadu Sabau - gp0 92*1ea5792aSRadu Sabau - gp1 93*1ea5792aSRadu Sabau - gp2 94*1ea5792aSRadu Sabau - gp3 95*1ea5792aSRadu Sabau 96*1ea5792aSRadu Sabau gpio-controller: true 97*1ea5792aSRadu Sabau 98*1ea5792aSRadu Sabau '#gpio-cells': 99*1ea5792aSRadu Sabau const: 2 100*1ea5792aSRadu Sabau 101*1ea5792aSRadu Sabau '#trigger-source-cells': 102*1ea5792aSRadu Sabau description: 103*1ea5792aSRadu Sabau This node can act as a trigger source. The single cell in a consumer 104*1ea5792aSRadu Sabau reference specifies the GP pin number (0-3) used as the trigger output. 105*1ea5792aSRadu Sabau const: 1 106*1ea5792aSRadu Sabau 107*1ea5792aSRadu Sabaurequired: 108*1ea5792aSRadu Sabau - compatible 109*1ea5792aSRadu Sabau - reg 110*1ea5792aSRadu Sabau - avdd-supply 111*1ea5792aSRadu Sabau - vio-supply 112*1ea5792aSRadu Sabau 113*1ea5792aSRadu SabauallOf: 114*1ea5792aSRadu Sabau # vdd-supply and ldo-in-supply are mutually exclusive, one is required: 115*1ea5792aSRadu Sabau # either an external 1.8V VDD is provided or the internal LDO is fed from 116*1ea5792aSRadu Sabau # ldo-in-supply to generate VDD. 117*1ea5792aSRadu Sabau - oneOf: 118*1ea5792aSRadu Sabau - required: 119*1ea5792aSRadu Sabau - vdd-supply 120*1ea5792aSRadu Sabau - required: 121*1ea5792aSRadu Sabau - ldo-in-supply 122*1ea5792aSRadu Sabau # ref-supply and refin-supply are mutually exclusive, one is required 123*1ea5792aSRadu Sabau - oneOf: 124*1ea5792aSRadu Sabau - required: 125*1ea5792aSRadu Sabau - ref-supply 126*1ea5792aSRadu Sabau - required: 127*1ea5792aSRadu Sabau - refin-supply 128*1ea5792aSRadu Sabau 129*1ea5792aSRadu SabauunevaluatedProperties: false 130*1ea5792aSRadu Sabau 131*1ea5792aSRadu Sabauexamples: 132*1ea5792aSRadu Sabau - | 133*1ea5792aSRadu Sabau #include <dt-bindings/gpio/gpio.h> 134*1ea5792aSRadu Sabau /* AD4692 in CNV Burst Mode with SPI offload */ 135*1ea5792aSRadu Sabau spi { 136*1ea5792aSRadu Sabau #address-cells = <1>; 137*1ea5792aSRadu Sabau #size-cells = <0>; 138*1ea5792aSRadu Sabau 139*1ea5792aSRadu Sabau adc@0 { 140*1ea5792aSRadu Sabau compatible = "adi,ad4692"; 141*1ea5792aSRadu Sabau reg = <0>; 142*1ea5792aSRadu Sabau spi-cpol; 143*1ea5792aSRadu Sabau spi-cpha; 144*1ea5792aSRadu Sabau spi-max-frequency = <40000000>; 145*1ea5792aSRadu Sabau 146*1ea5792aSRadu Sabau avdd-supply = <&avdd_supply>; 147*1ea5792aSRadu Sabau ldo-in-supply = <&avdd_supply>; 148*1ea5792aSRadu Sabau vio-supply = <&vio_supply>; 149*1ea5792aSRadu Sabau ref-supply = <&ref_5v>; 150*1ea5792aSRadu Sabau 151*1ea5792aSRadu Sabau reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; 152*1ea5792aSRadu Sabau 153*1ea5792aSRadu Sabau pwms = <&pwm_gen 0 0>; 154*1ea5792aSRadu Sabau 155*1ea5792aSRadu Sabau #trigger-source-cells = <1>; 156*1ea5792aSRadu Sabau }; 157*1ea5792aSRadu Sabau }; 158*1ea5792aSRadu Sabau 159*1ea5792aSRadu Sabau - | 160*1ea5792aSRadu Sabau #include <dt-bindings/gpio/gpio.h> 161*1ea5792aSRadu Sabau /* AD4692 in Manual Mode (CNV tied to SPI CS) */ 162*1ea5792aSRadu Sabau spi { 163*1ea5792aSRadu Sabau #address-cells = <1>; 164*1ea5792aSRadu Sabau #size-cells = <0>; 165*1ea5792aSRadu Sabau 166*1ea5792aSRadu Sabau adc@0 { 167*1ea5792aSRadu Sabau compatible = "adi,ad4692"; 168*1ea5792aSRadu Sabau reg = <0>; 169*1ea5792aSRadu Sabau spi-cpol; 170*1ea5792aSRadu Sabau spi-cpha; 171*1ea5792aSRadu Sabau spi-max-frequency = <31250000>; 172*1ea5792aSRadu Sabau 173*1ea5792aSRadu Sabau avdd-supply = <&avdd_supply>; 174*1ea5792aSRadu Sabau ldo-in-supply = <&avdd_supply>; 175*1ea5792aSRadu Sabau vio-supply = <&vio_supply>; 176*1ea5792aSRadu Sabau refin-supply = <&refin_supply>; 177*1ea5792aSRadu Sabau 178*1ea5792aSRadu Sabau reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; 179*1ea5792aSRadu Sabau }; 180*1ea5792aSRadu Sabau }; 181