xref: /linux/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml (revision 67f8bc848ee31831336bd478e57d2f993551902e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c-1.0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AMD I3C master
8
9maintainers:
10  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11  - Shubham Patil <shubhamsanjay.patil@amd.com>
12
13description:
14  The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compatible
15  with the MIPI I3C Specification v1.1.1. The design includes bidirectional I/O
16  buffers that implement open collector drivers for the SDA and SCL signals.
17  External pull-up resistors are required to properly hold the bus at a Logic-1
18  level when the drivers are released.
19
20  For more details, please see https://docs.amd.com/r/en-US/pg439-axi-i3c
21
22properties:
23  compatible:
24    const: xlnx,axi-i3c-1.0
25
26  reg:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35required:
36  - compatible
37  - reg
38  - clocks
39
40allOf:
41  - $ref: i3c.yaml#
42
43unevaluatedProperties: false
44
45examples:
46  - |
47    #include <dt-bindings/interrupt-controller/arm-gic.h>
48
49    i3c@80000000 {
50        compatible = "xlnx,axi-i3c-1.0";
51        reg = <0x80000000 0x10000>;
52        clocks = <&zynqmp_clk 71>;
53        interrupt-parent = <&imux>;
54        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
55        #address-cells = <3>;
56        #size-cells = <0>;
57    };
58...
59