1*aa66eb12SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*aa66eb12SRob Herring (Arm)%YAML 1.2 3*aa66eb12SRob Herring (Arm)--- 4*aa66eb12SRob Herring (Arm)$id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml# 5*aa66eb12SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*aa66eb12SRob Herring (Arm) 7*aa66eb12SRob Herring (Arm)title: ST Microelectronics SPEAr SPI CS GPIO Controller 8*aa66eb12SRob Herring (Arm) 9*aa66eb12SRob Herring (Arm)maintainers: 10*aa66eb12SRob Herring (Arm) - Viresh Kumar <vireshk@kernel.org> 11*aa66eb12SRob Herring (Arm) 12*aa66eb12SRob Herring (Arm)description: > 13*aa66eb12SRob Herring (Arm) SPEAr platform provides a provision to control chipselects of ARM PL022 Prime 14*aa66eb12SRob Herring (Arm) Cell spi controller through its system registers, which otherwise remains 15*aa66eb12SRob Herring (Arm) under PL022 control. If chipselect remain under PL022 control then they would 16*aa66eb12SRob Herring (Arm) be released as soon as transfer is over and TxFIFO becomes empty. This is not 17*aa66eb12SRob Herring (Arm) desired by some of the device protocols above spi which expect (multiple) 18*aa66eb12SRob Herring (Arm) transfers without releasing their chipselects. 19*aa66eb12SRob Herring (Arm) 20*aa66eb12SRob Herring (Arm) Chipselects can be controlled by software by turning them as GPIOs. SPEAr 21*aa66eb12SRob Herring (Arm) provides another interface through system registers through which software can 22*aa66eb12SRob Herring (Arm) directly control each PL022 chipselect. Hence, it is natural for SPEAr to 23*aa66eb12SRob Herring (Arm) export the control of this interface as gpio. 24*aa66eb12SRob Herring (Arm) 25*aa66eb12SRob Herring (Arm)properties: 26*aa66eb12SRob Herring (Arm) compatible: 27*aa66eb12SRob Herring (Arm) const: st,spear-spics-gpio 28*aa66eb12SRob Herring (Arm) 29*aa66eb12SRob Herring (Arm) reg: 30*aa66eb12SRob Herring (Arm) maxItems: 1 31*aa66eb12SRob Herring (Arm) 32*aa66eb12SRob Herring (Arm) gpio-controller: true 33*aa66eb12SRob Herring (Arm) 34*aa66eb12SRob Herring (Arm) '#gpio-cells': 35*aa66eb12SRob Herring (Arm) const: 2 36*aa66eb12SRob Herring (Arm) 37*aa66eb12SRob Herring (Arm) st-spics,peripcfg-reg: 38*aa66eb12SRob Herring (Arm) description: Offset of the peripcfg register. 39*aa66eb12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 40*aa66eb12SRob Herring (Arm) 41*aa66eb12SRob Herring (Arm) st-spics,sw-enable-bit: 42*aa66eb12SRob Herring (Arm) description: Bit offset to enable software chipselect control. 43*aa66eb12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 44*aa66eb12SRob Herring (Arm) 45*aa66eb12SRob Herring (Arm) st-spics,cs-value-bit: 46*aa66eb12SRob Herring (Arm) description: Bit offset to drive chipselect low or high. 47*aa66eb12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 48*aa66eb12SRob Herring (Arm) 49*aa66eb12SRob Herring (Arm) st-spics,cs-enable-mask: 50*aa66eb12SRob Herring (Arm) description: Bitmask selecting which chipselects to enable. 51*aa66eb12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 52*aa66eb12SRob Herring (Arm) 53*aa66eb12SRob Herring (Arm) st-spics,cs-enable-shift: 54*aa66eb12SRob Herring (Arm) description: Bit shift for programming chipselect number. 55*aa66eb12SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/uint32 56*aa66eb12SRob Herring (Arm) 57*aa66eb12SRob Herring (Arm)required: 58*aa66eb12SRob Herring (Arm) - compatible 59*aa66eb12SRob Herring (Arm) - reg 60*aa66eb12SRob Herring (Arm) - gpio-controller 61*aa66eb12SRob Herring (Arm) - '#gpio-cells' 62*aa66eb12SRob Herring (Arm) - st-spics,peripcfg-reg 63*aa66eb12SRob Herring (Arm) - st-spics,sw-enable-bit 64*aa66eb12SRob Herring (Arm) - st-spics,cs-value-bit 65*aa66eb12SRob Herring (Arm) - st-spics,cs-enable-mask 66*aa66eb12SRob Herring (Arm) - st-spics,cs-enable-shift 67*aa66eb12SRob Herring (Arm) 68*aa66eb12SRob Herring (Arm)additionalProperties: false 69*aa66eb12SRob Herring (Arm) 70*aa66eb12SRob Herring (Arm)examples: 71*aa66eb12SRob Herring (Arm) - | 72*aa66eb12SRob Herring (Arm) gpio@e0700000 { 73*aa66eb12SRob Herring (Arm) compatible = "st,spear-spics-gpio"; 74*aa66eb12SRob Herring (Arm) reg = <0xe0700000 0x1000>; 75*aa66eb12SRob Herring (Arm) st-spics,peripcfg-reg = <0x3b0>; 76*aa66eb12SRob Herring (Arm) st-spics,sw-enable-bit = <12>; 77*aa66eb12SRob Herring (Arm) st-spics,cs-value-bit = <11>; 78*aa66eb12SRob Herring (Arm) st-spics,cs-enable-mask = <3>; 79*aa66eb12SRob Herring (Arm) st-spics,cs-enable-shift = <8>; 80*aa66eb12SRob Herring (Arm) gpio-controller; 81*aa66eb12SRob Herring (Arm) #gpio-cells = <2>; 82*aa66eb12SRob Herring (Arm) }; 83