1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/fsl,mpc8323-qe-pario-bank.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank 8 9maintainers: 10 - Christophe Leroy <christophe.leroy@csgroup.eu> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - fsl,mpc8360-qe-pario-bank 18 - fsl,mpc8569-qe-pario-bank 19 - const: fsl,mpc8323-qe-pario-bank 20 - const: fsl,mpc8323-qe-pario-bank 21 22 reg: 23 maxItems: 1 24 25 gpio-controller: true 26 27 "#gpio-cells": 28 const: 2 29 30 "#address-cells": 31 const: 0 32 33 "#interrupt-cells": 34 const: 2 35 36 interrupt-map: 37 description: | 38 Specifies the mapping of GPIO lines to the parent interrupt controller, as the 39 GPIO controller does not do interrupt handling itself. 40 41required: 42 - compatible 43 - reg 44 - gpio-controller 45 - "#gpio-cells" 46 47additionalProperties: false 48 49examples: 50 - | 51 #include <dt-bindings/interrupt-controller/irq.h> 52 53 gpio-controller@1400 { 54 compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank"; 55 reg = <0x1400 0x18>; 56 gpio-controller; 57 #gpio-cells = <2>; 58 }; 59 60 gpio-controller@1418 { 61 compatible = "fsl,mpc8323-qe-pario-bank"; 62 reg = <0x1418 0x18>; 63 gpio-controller; 64 #gpio-cells = <2>; 65 #address-cells = <0>; 66 #interrupt-cells = <2>; 67 interrupt-map = < 68 7 IRQ_TYPE_EDGE_FALLING &pic 4 IRQ_TYPE_EDGE_FALLING 69 7 IRQ_TYPE_EDGE_BOTH &pic 4 IRQ_TYPE_EDGE_BOTH 70 7 0 &pic 4 IRQ_TYPE_NONE 71 72 9 IRQ_TYPE_EDGE_FALLING &pic 5 IRQ_TYPE_EDGE_FALLING 73 9 IRQ_TYPE_EDGE_BOTH &pic 5 IRQ_TYPE_EDGE_BOTH 74 9 0 &pic 5 IRQ_TYPE_NONE 75 76 25 IRQ_TYPE_EDGE_FALLING &pic 6 IRQ_TYPE_EDGE_FALLING 77 25 IRQ_TYPE_EDGE_BOTH &pic 6 IRQ_TYPE_EDGE_BOTH 78 25 0 &pic 6 IRQ_TYPE_NONE 79 80 27 IRQ_TYPE_EDGE_FALLING &pic 7 IRQ_TYPE_EDGE_FALLING 81 27 IRQ_TYPE_EDGE_BOTH &pic 7 IRQ_TYPE_EDGE_BOTH 82 27 0 &pic 7 IRQ_TYPE_NONE 83 >; 84 }; 85