xref: /linux/Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml (revision 24f171c7e145f43b9f187578e89b0982ce87e54c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Lattice iCE40 FPGA Manager
8
9maintainers:
10  - Joel Holdsworth <joel@airwebreathe.org.uk>
11
12properties:
13  compatible:
14    const: lattice,ice40-fpga-mgr
15
16  reg:
17    maxItems: 1
18
19  spi-max-frequency:
20    minimum: 1000000
21    maximum: 25000000
22
23  cdone-gpios:
24    maxItems: 1
25    description: GPIO input connected to CDONE pin
26
27  reset-gpios:
28    maxItems: 1
29    description:
30      Active-low GPIO output connected to CRESET_B pin. Note that unless the
31      GPIO is held low during startup, the FPGA will enter Master SPI mode and
32      drive SCK with a clock signal potentially jamming other devices on the bus
33      until the firmware is loaded.
34
35required:
36  - compatible
37  - reg
38  - spi-max-frequency
39  - cdone-gpios
40  - reset-gpios
41
42additionalProperties: false
43
44examples:
45  - |
46    #include <dt-bindings/gpio/gpio.h>
47
48    spi {
49        #address-cells = <1>;
50        #size-cells = <0>;
51
52        fpga@0 {
53            compatible = "lattice,ice40-fpga-mgr";
54            reg = <0>;
55            spi-max-frequency = <1000000>;
56            cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
57            reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
58        };
59    };
60