xref: /linux/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC display controller (VOP2)
8
9description:
10  VOP2 (Video Output Processor v2) is the display controller for the Rockchip
11  series of SoCs which transfers the image data from a video memory buffer to
12  an external LCD interface.
13
14maintainers:
15  - Sandy Huang <hjc@rock-chips.com>
16  - Heiko Stuebner <heiko@sntech.de>
17  - Andy Yan <andyshrk@163.com>
18
19properties:
20  compatible:
21    enum:
22      - rockchip,rk3566-vop
23      - rockchip,rk3568-vop
24      - rockchip,rk3576-vop
25      - rockchip,rk3588-vop
26
27  reg:
28    items:
29      - description:
30          Must contain one entry corresponding to the base address and length
31          of the register space.
32      - description:
33          Can optionally contain a second entry corresponding to the CRTC gamma
34          LUT address.
35
36  reg-names:
37    items:
38      - const: vop
39      - const: gamma-lut
40
41  interrupts:
42    minItems: 1
43    maxItems: 4
44    description:
45      For VOP version under rk3576, the interrupt is shared by several interrupt
46      sources, such as frame start (VSYNC), line flag and other interrupt status.
47      For VOP version from rk3576 there is a system interrupt for bus error, and
48      every video port has it's independent interrupts for vsync and other video
49      port related error interrupts.
50
51  interrupt-names:
52    items:
53      - const: sys
54      - const: vp0
55      - const: vp1
56      - const: vp2
57
58  # See compatible-specific constraints below.
59  clocks:
60    minItems: 5
61    items:
62      - description: Clock for ddr buffer transfer via axi.
63      - description: Clock for the ahb bus to R/W the regs.
64      - description: Pixel clock for video port 0.
65      - description: Pixel clock for video port 1.
66      - description: Pixel clock for video port 2.
67      - {}
68      - {}
69      - {}
70      - {}
71
72  clock-names:
73    minItems: 5
74    items:
75      - const: aclk
76      - const: hclk
77      - const: dclk_vp0
78      - const: dclk_vp1
79      - const: dclk_vp2
80      - {}
81      - {}
82      - {}
83      - {}
84
85  rockchip,grf:
86    $ref: /schemas/types.yaml#/definitions/phandle
87    description:
88      Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
89      also used for query vop memory bisr enable status, etc.
90
91  rockchip,vo1-grf:
92    $ref: /schemas/types.yaml#/definitions/phandle
93    description:
94      Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
95      on rk3588.
96
97  rockchip,vop-grf:
98    $ref: /schemas/types.yaml#/definitions/phandle
99    description:
100      Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
101
102  rockchip,pmu:
103    $ref: /schemas/types.yaml#/definitions/phandle
104    description:
105      Phandle to PMU GRF used for query vop memory bisr status on rk3588.
106
107  ports:
108    $ref: /schemas/graph.yaml#/properties/ports
109
110    patternProperties:
111      "^port@[0-3]$":
112        $ref: /schemas/graph.yaml#/properties/port
113        description: Output endpoint of VP0/1/2/3.
114
115    required:
116      - port@0
117
118    unevaluatedProperties: false
119
120  iommus:
121    maxItems: 1
122
123  power-domains:
124    maxItems: 1
125
126required:
127  - compatible
128  - reg
129  - reg-names
130  - interrupts
131  - clocks
132  - clock-names
133  - ports
134
135allOf:
136  - if:
137      properties:
138        compatible:
139          contains:
140            enum:
141              - rockchip,rk3566-vop
142              - rockchip,rk3568-vop
143    then:
144      properties:
145        clocks:
146          maxItems: 5
147
148        clock-names:
149          maxItems: 5
150
151        interrupts:
152          maxItems: 1
153
154        interrupt-names: false
155
156        ports:
157          required:
158            - port@0
159            - port@1
160            - port@2
161
162        rockchip,vo1-grf: false
163        rockchip,vop-grf: false
164        rockchip,pmu: false
165
166      required:
167        - rockchip,grf
168
169  - if:
170      properties:
171        compatible:
172          contains:
173            enum:
174              - rockchip,rk3576-vop
175    then:
176      properties:
177        clocks:
178          minItems: 5
179          items:
180            - {}
181            - {}
182            - {}
183            - {}
184            - {}
185            - description: Alternative pixel clock provided by HDMI PHY PLL.
186
187        clock-names:
188          minItems: 5
189          items:
190            - {}
191            - {}
192            - {}
193            - {}
194            - {}
195            - const: pll_hdmiphy0
196
197        interrupts:
198          minItems: 4
199
200        interrupt-names:
201          minItems: 4
202
203        ports:
204          required:
205            - port@0
206            - port@1
207            - port@2
208
209        rockchip,vo1-grf: false
210        rockchip,vop-grf: false
211
212      required:
213        - rockchip,grf
214        - rockchip,pmu
215
216  - if:
217      properties:
218        compatible:
219          contains:
220            const: rockchip,rk3588-vop
221    then:
222      properties:
223        clocks:
224          minItems: 7
225          items:
226            - {}
227            - {}
228            - {}
229            - {}
230            - {}
231            - description: Pixel clock for video port 3.
232            - description: Peripheral(vop grf/dsi) clock.
233            - description: Alternative pixel clock provided by HDMI0 PHY PLL.
234            - description: Alternative pixel clock provided by HDMI1 PHY PLL.
235
236        clock-names:
237          minItems: 7
238          items:
239            - {}
240            - {}
241            - {}
242            - {}
243            - {}
244            - const: dclk_vp3
245            - const: pclk_vop
246            - const: pll_hdmiphy0
247            - const: pll_hdmiphy1
248
249        interrupts:
250          maxItems: 1
251
252        interrupt-names: false
253
254        ports:
255          required:
256            - port@0
257            - port@1
258            - port@2
259            - port@3
260
261      required:
262        - rockchip,grf
263        - rockchip,vo1-grf
264        - rockchip,vop-grf
265        - rockchip,pmu
266
267additionalProperties: false
268
269examples:
270  - |
271        #include <dt-bindings/clock/rk3568-cru.h>
272        #include <dt-bindings/interrupt-controller/arm-gic.h>
273        #include <dt-bindings/power/rk3568-power.h>
274        bus {
275            #address-cells = <2>;
276            #size-cells = <2>;
277            vop: vop@fe040000 {
278                compatible = "rockchip,rk3568-vop";
279                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
280                reg-names = "vop", "gamma-lut";
281                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
282                clocks = <&cru ACLK_VOP>,
283                         <&cru HCLK_VOP>,
284                         <&cru DCLK_VOP0>,
285                         <&cru DCLK_VOP1>,
286                         <&cru DCLK_VOP2>;
287                clock-names = "aclk",
288                              "hclk",
289                              "dclk_vp0",
290                              "dclk_vp1",
291                              "dclk_vp2";
292                power-domains = <&power RK3568_PD_VO>;
293                rockchip,grf = <&grf>;
294                iommus = <&vop_mmu>;
295                vop_out: ports {
296                    #address-cells = <1>;
297                    #size-cells = <0>;
298                    vp0: port@0 {
299                        reg = <0>;
300                        #address-cells = <1>;
301                        #size-cells = <0>;
302                    };
303                    vp1: port@1 {
304                        reg = <1>;
305                        #address-cells = <1>;
306                        #size-cells = <0>;
307                    };
308                    vp2: port@2 {
309                        reg = <2>;
310                        #address-cells = <1>;
311                        #size-cells = <0>;
312                    };
313                };
314            };
315        };
316