1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip SoC display controller (VOP2) 8 9description: 10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip 11 series of SoCs which transfers the image data from a video memory buffer to 12 an external LCD interface. 13 14maintainers: 15 - Sandy Huang <hjc@rock-chips.com> 16 - Heiko Stuebner <heiko@sntech.de> 17 18properties: 19 compatible: 20 enum: 21 - rockchip,rk3566-vop 22 - rockchip,rk3568-vop 23 - rockchip,rk3588-vop 24 25 reg: 26 items: 27 - description: 28 Must contain one entry corresponding to the base address and length 29 of the register space. 30 - description: 31 Can optionally contain a second entry corresponding to the CRTC gamma 32 LUT address. 33 34 reg-names: 35 items: 36 - const: vop 37 - const: gamma-lut 38 39 interrupts: 40 maxItems: 1 41 description: 42 The VOP interrupt is shared by several interrupt sources, such as 43 frame start (VSYNC), line flag and other status interrupts. 44 45 # See compatible-specific constraints below. 46 clocks: 47 minItems: 5 48 items: 49 - description: Clock for ddr buffer transfer via axi. 50 - description: Clock for the ahb bus to R/W the regs. 51 - description: Pixel clock for video port 0. 52 - description: Pixel clock for video port 1. 53 - description: Pixel clock for video port 2. 54 - description: Pixel clock for video port 3. 55 - description: Peripheral(vop grf/dsi) clock. 56 57 clock-names: 58 minItems: 5 59 items: 60 - const: aclk 61 - const: hclk 62 - const: dclk_vp0 63 - const: dclk_vp1 64 - const: dclk_vp2 65 - const: dclk_vp3 66 - const: pclk_vop 67 68 rockchip,grf: 69 $ref: /schemas/types.yaml#/definitions/phandle 70 description: 71 Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI, 72 also used for query vop memory bisr enable status, etc. 73 74 rockchip,vo1-grf: 75 $ref: /schemas/types.yaml#/definitions/phandle 76 description: 77 Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi 78 on rk3588. 79 80 rockchip,vop-grf: 81 $ref: /schemas/types.yaml#/definitions/phandle 82 description: 83 Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp. 84 85 rockchip,pmu: 86 $ref: /schemas/types.yaml#/definitions/phandle 87 description: 88 Phandle to PMU GRF used for query vop memory bisr status on rk3588. 89 90 ports: 91 $ref: /schemas/graph.yaml#/properties/ports 92 93 patternProperties: 94 "^port@[0-3]$": 95 $ref: /schemas/graph.yaml#/properties/port 96 description: Output endpoint of VP0/1/2/3. 97 98 required: 99 - port@0 100 101 unevaluatedProperties: false 102 103 iommus: 104 maxItems: 1 105 106 power-domains: 107 maxItems: 1 108 109required: 110 - compatible 111 - reg 112 - reg-names 113 - interrupts 114 - clocks 115 - clock-names 116 - ports 117 118allOf: 119 - if: 120 properties: 121 compatible: 122 contains: 123 const: rockchip,rk3588-vop 124 then: 125 properties: 126 clocks: 127 minItems: 7 128 clock-names: 129 minItems: 7 130 131 ports: 132 required: 133 - port@0 134 - port@1 135 - port@2 136 - port@3 137 138 required: 139 - rockchip,grf 140 - rockchip,vo1-grf 141 - rockchip,vop-grf 142 - rockchip,pmu 143 144 else: 145 properties: 146 rockchip,vo1-grf: false 147 rockchip,vop-grf: false 148 rockchip,pmu: false 149 150 clocks: 151 maxItems: 5 152 clock-names: 153 maxItems: 5 154 155 ports: 156 required: 157 - port@0 158 - port@1 159 - port@2 160 161additionalProperties: false 162 163examples: 164 - | 165 #include <dt-bindings/clock/rk3568-cru.h> 166 #include <dt-bindings/interrupt-controller/arm-gic.h> 167 #include <dt-bindings/power/rk3568-power.h> 168 bus { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 vop: vop@fe040000 { 172 compatible = "rockchip,rk3568-vop"; 173 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 174 reg-names = "vop", "gamma-lut"; 175 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cru ACLK_VOP>, 177 <&cru HCLK_VOP>, 178 <&cru DCLK_VOP0>, 179 <&cru DCLK_VOP1>, 180 <&cru DCLK_VOP2>; 181 clock-names = "aclk", 182 "hclk", 183 "dclk_vp0", 184 "dclk_vp1", 185 "dclk_vp2"; 186 power-domains = <&power RK3568_PD_VO>; 187 iommus = <&vop_mmu>; 188 vop_out: ports { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 vp0: port@0 { 192 reg = <0>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 }; 196 vp1: port@1 { 197 reg = <1>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 }; 201 vp2: port@2 { 202 reg = <2>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 }; 206 }; 207 }; 208 }; 209