1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip SoC display controller (VOP2) 8 9description: 10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip 11 series of SoCs which transfers the image data from a video memory buffer to 12 an external LCD interface. 13 14maintainers: 15 - Sandy Huang <hjc@rock-chips.com> 16 - Heiko Stuebner <heiko@sntech.de> 17 - Andy Yan <andyshrk@163.com> 18 19properties: 20 compatible: 21 enum: 22 - rockchip,rk3566-vop 23 - rockchip,rk3568-vop 24 - rockchip,rk3576-vop 25 - rockchip,rk3588-vop 26 27 reg: 28 items: 29 - description: 30 Must contain one entry corresponding to the base address and length 31 of the register space. 32 - description: 33 Can optionally contain a second entry corresponding to the CRTC gamma 34 LUT address. 35 36 reg-names: 37 items: 38 - const: vop 39 - const: gamma-lut 40 41 interrupts: 42 minItems: 1 43 maxItems: 4 44 description: 45 For VOP version under rk3576, the interrupt is shared by several interrupt 46 sources, such as frame start (VSYNC), line flag and other interrupt status. 47 For VOP version from rk3576 there is a system interrupt for bus error, and 48 every video port has it's independent interrupts for vsync and other video 49 port related error interrupts. 50 51 interrupt-names: 52 items: 53 - const: sys 54 - const: vp0 55 - const: vp1 56 - const: vp2 57 58 # See compatible-specific constraints below. 59 clocks: 60 minItems: 5 61 items: 62 - description: Clock for ddr buffer transfer via axi. 63 - description: Clock for the ahb bus to R/W the regs. 64 - description: Pixel clock for video port 0. 65 - description: Pixel clock for video port 1. 66 - description: Pixel clock for video port 2. 67 - description: Pixel clock for video port 3. 68 - description: Peripheral(vop grf/dsi) clock. 69 - description: Alternative pixel clock provided by HDMI0 PHY PLL. 70 - description: Alternative pixel clock provided by HDMI1 PHY PLL. 71 72 clock-names: 73 minItems: 5 74 items: 75 - const: aclk 76 - const: hclk 77 - const: dclk_vp0 78 - const: dclk_vp1 79 - const: dclk_vp2 80 - const: dclk_vp3 81 - const: pclk_vop 82 - const: pll_hdmiphy0 83 - const: pll_hdmiphy1 84 85 rockchip,grf: 86 $ref: /schemas/types.yaml#/definitions/phandle 87 description: 88 Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI, 89 also used for query vop memory bisr enable status, etc. 90 91 rockchip,vo1-grf: 92 $ref: /schemas/types.yaml#/definitions/phandle 93 description: 94 Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi 95 on rk3588. 96 97 rockchip,vop-grf: 98 $ref: /schemas/types.yaml#/definitions/phandle 99 description: 100 Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp. 101 102 rockchip,pmu: 103 $ref: /schemas/types.yaml#/definitions/phandle 104 description: 105 Phandle to PMU GRF used for query vop memory bisr status on rk3588. 106 107 ports: 108 $ref: /schemas/graph.yaml#/properties/ports 109 110 patternProperties: 111 "^port@[0-3]$": 112 $ref: /schemas/graph.yaml#/properties/port 113 description: Output endpoint of VP0/1/2/3. 114 115 required: 116 - port@0 117 118 unevaluatedProperties: false 119 120 iommus: 121 maxItems: 1 122 123 power-domains: 124 maxItems: 1 125 126required: 127 - compatible 128 - reg 129 - reg-names 130 - interrupts 131 - clocks 132 - clock-names 133 - ports 134 135allOf: 136 - if: 137 properties: 138 compatible: 139 contains: 140 enum: 141 - rockchip,rk3566-vop 142 - rockchip,rk3568-vop 143 then: 144 properties: 145 clocks: 146 maxItems: 5 147 148 clock-names: 149 maxItems: 5 150 151 interrupts: 152 maxItems: 1 153 154 interrupt-names: false 155 156 ports: 157 required: 158 - port@0 159 - port@1 160 - port@2 161 162 rockchip,vo1-grf: false 163 rockchip,vop-grf: false 164 rockchip,pmu: false 165 166 required: 167 - rockchip,grf 168 169 - if: 170 properties: 171 compatible: 172 contains: 173 enum: 174 - rockchip,rk3576-vop 175 then: 176 properties: 177 clocks: 178 maxItems: 5 179 180 clock-names: 181 maxItems: 5 182 183 interrupts: 184 minItems: 4 185 186 interrupt-names: 187 minItems: 4 188 189 ports: 190 required: 191 - port@0 192 - port@1 193 - port@2 194 195 rockchip,vo1-grf: false 196 rockchip,vop-grf: false 197 198 required: 199 - rockchip,grf 200 - rockchip,pmu 201 202 - if: 203 properties: 204 compatible: 205 contains: 206 const: rockchip,rk3588-vop 207 then: 208 properties: 209 clocks: 210 minItems: 7 211 maxItems: 9 212 213 clock-names: 214 minItems: 7 215 maxItems: 9 216 217 interrupts: 218 maxItems: 1 219 220 interrupt-names: false 221 222 ports: 223 required: 224 - port@0 225 - port@1 226 - port@2 227 - port@3 228 229 required: 230 - rockchip,grf 231 - rockchip,vo1-grf 232 - rockchip,vop-grf 233 - rockchip,pmu 234 235additionalProperties: false 236 237examples: 238 - | 239 #include <dt-bindings/clock/rk3568-cru.h> 240 #include <dt-bindings/interrupt-controller/arm-gic.h> 241 #include <dt-bindings/power/rk3568-power.h> 242 bus { 243 #address-cells = <2>; 244 #size-cells = <2>; 245 vop: vop@fe040000 { 246 compatible = "rockchip,rk3568-vop"; 247 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 248 reg-names = "vop", "gamma-lut"; 249 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&cru ACLK_VOP>, 251 <&cru HCLK_VOP>, 252 <&cru DCLK_VOP0>, 253 <&cru DCLK_VOP1>, 254 <&cru DCLK_VOP2>; 255 clock-names = "aclk", 256 "hclk", 257 "dclk_vp0", 258 "dclk_vp1", 259 "dclk_vp2"; 260 power-domains = <&power RK3568_PD_VO>; 261 rockchip,grf = <&grf>; 262 iommus = <&vop_mmu>; 263 vop_out: ports { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 vp0: port@0 { 267 reg = <0>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 }; 271 vp1: port@1 { 272 reg = <1>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 vp2: port@2 { 277 reg = <2>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 }; 281 }; 282 }; 283 }; 284