xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml (revision 4b01712311c6e209137c4fa3e7d7920ec509456a) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8650 Display DPU
8
9maintainers:
10  - Neil Armstrong <neil.armstrong@linaro.org>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15  compatible:
16    enum:
17      - qcom,sa8775p-dpu
18      - qcom,sm8650-dpu
19      - qcom,x1e80100-dpu
20
21  reg:
22    items:
23      - description: Address offset and size for mdp register set
24      - description: Address offset and size for vbif register set
25
26  reg-names:
27    items:
28      - const: mdp
29      - const: vbif
30
31  clocks:
32    items:
33      - description: Display hf axi
34      - description: Display MDSS ahb
35      - description: Display lut
36      - description: Display core
37      - description: Display vsync
38
39  clock-names:
40    items:
41      - const: nrt_bus
42      - const: iface
43      - const: lut
44      - const: core
45      - const: vsync
46
47required:
48  - compatible
49  - reg
50  - reg-names
51  - clocks
52  - clock-names
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/interrupt-controller/arm-gic.h>
59    #include <dt-bindings/power/qcom,rpmhpd.h>
60
61    display-controller@ae01000 {
62        compatible = "qcom,sm8650-dpu";
63        reg = <0x0ae01000 0x8f000>,
64              <0x0aeb0000 0x2008>;
65        reg-names = "mdp", "vbif";
66
67        clocks = <&gcc_axi_clk>,
68                 <&dispcc_ahb_clk>,
69                 <&dispcc_mdp_lut_clk>,
70                 <&dispcc_mdp_clk>,
71                 <&dispcc_vsync_clk>;
72        clock-names = "nrt_bus",
73                      "iface",
74                      "lut",
75                      "core",
76                      "vsync";
77
78        assigned-clocks = <&dispcc_vsync_clk>;
79        assigned-clock-rates = <19200000>;
80
81        operating-points-v2 = <&mdp_opp_table>;
82        power-domains = <&rpmhpd RPMHPD_MMCX>;
83
84        interrupt-parent = <&mdss>;
85        interrupts = <0>;
86
87        ports {
88            #address-cells = <1>;
89            #size-cells = <0>;
90
91            port@0 {
92                reg = <0>;
93                dpu_intf1_out: endpoint {
94                    remote-endpoint = <&dsi0_in>;
95                };
96            };
97
98            port@1 {
99                reg = <1>;
100                dpu_intf2_out: endpoint {
101                    remote-endpoint = <&dsi1_in>;
102                };
103            };
104        };
105
106        mdp_opp_table: opp-table {
107            compatible = "operating-points-v2";
108
109            opp-200000000 {
110                opp-hz = /bits/ 64 <200000000>;
111                required-opps = <&rpmhpd_opp_low_svs>;
112            };
113
114            opp-325000000 {
115                opp-hz = /bits/ 64 <325000000>;
116                required-opps = <&rpmhpd_opp_svs>;
117            };
118
119            opp-375000000 {
120                opp-hz = /bits/ 64 <375000000>;
121                required-opps = <&rpmhpd_opp_svs_l1>;
122            };
123
124            opp-514000000 {
125                opp-hz = /bits/ 64 <514000000>;
126                required-opps = <&rpmhpd_opp_nom>;
127            };
128        };
129    };
130...
131