1*701da286SLi Liu# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*701da286SLi Liu%YAML 1.2 3*701da286SLi Liu--- 4*701da286SLi Liu$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml# 5*701da286SLi Liu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*701da286SLi Liu 7*701da286SLi Liutitle: Qualcomm SM6150 Display DPU 8*701da286SLi Liu 9*701da286SLi Liumaintainers: 10*701da286SLi Liu - Abhinav Kumar <quic_abhinavk@quicinc.com> 11*701da286SLi Liu - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 12*701da286SLi Liu 13*701da286SLi Liu$ref: /schemas/display/msm/dpu-common.yaml# 14*701da286SLi Liu 15*701da286SLi Liuproperties: 16*701da286SLi Liu compatible: 17*701da286SLi Liu const: qcom,sm6150-dpu 18*701da286SLi Liu 19*701da286SLi Liu reg: 20*701da286SLi Liu items: 21*701da286SLi Liu - description: Address offset and size for mdp register set 22*701da286SLi Liu - description: Address offset and size for vbif register set 23*701da286SLi Liu 24*701da286SLi Liu reg-names: 25*701da286SLi Liu items: 26*701da286SLi Liu - const: mdp 27*701da286SLi Liu - const: vbif 28*701da286SLi Liu 29*701da286SLi Liu clocks: 30*701da286SLi Liu items: 31*701da286SLi Liu - description: Display ahb clock 32*701da286SLi Liu - description: Display hf axi clock 33*701da286SLi Liu - description: Display core clock 34*701da286SLi Liu - description: Display vsync clock 35*701da286SLi Liu 36*701da286SLi Liu clock-names: 37*701da286SLi Liu items: 38*701da286SLi Liu - const: iface 39*701da286SLi Liu - const: bus 40*701da286SLi Liu - const: core 41*701da286SLi Liu - const: vsync 42*701da286SLi Liu 43*701da286SLi LiuunevaluatedProperties: false 44*701da286SLi Liu 45*701da286SLi Liuexamples: 46*701da286SLi Liu - | 47*701da286SLi Liu #include <dt-bindings/interrupt-controller/arm-gic.h> 48*701da286SLi Liu #include <dt-bindings/power/qcom,rpmhpd.h> 49*701da286SLi Liu 50*701da286SLi Liu display-controller@ae01000 { 51*701da286SLi Liu compatible = "qcom,sm6150-dpu"; 52*701da286SLi Liu reg = <0x0ae01000 0x8f000>, 53*701da286SLi Liu <0x0aeb0000 0x2008>; 54*701da286SLi Liu reg-names = "mdp", "vbif"; 55*701da286SLi Liu 56*701da286SLi Liu clocks = <&dispcc_mdss_ahb_clk>, 57*701da286SLi Liu <&gcc_disp_hf_axi_clk>, 58*701da286SLi Liu <&dispcc_mdss_mdp_clk>, 59*701da286SLi Liu <&dispcc_mdss_vsync_clk>; 60*701da286SLi Liu clock-names = "iface", "bus", "core", "vsync"; 61*701da286SLi Liu 62*701da286SLi Liu assigned-clocks = <&dispcc_mdss_vsync_clk>; 63*701da286SLi Liu assigned-clock-rates = <19200000>; 64*701da286SLi Liu 65*701da286SLi Liu operating-points-v2 = <&mdp_opp_table>; 66*701da286SLi Liu power-domains = <&rpmhpd RPMHPD_CX>; 67*701da286SLi Liu 68*701da286SLi Liu interrupt-parent = <&mdss>; 69*701da286SLi Liu interrupts = <0>; 70*701da286SLi Liu 71*701da286SLi Liu ports { 72*701da286SLi Liu #address-cells = <1>; 73*701da286SLi Liu #size-cells = <0>; 74*701da286SLi Liu 75*701da286SLi Liu port@0 { 76*701da286SLi Liu reg = <0>; 77*701da286SLi Liu dpu_intf0_out: endpoint { 78*701da286SLi Liu }; 79*701da286SLi Liu }; 80*701da286SLi Liu 81*701da286SLi Liu port@1 { 82*701da286SLi Liu reg = <1>; 83*701da286SLi Liu dpu_intf1_out: endpoint { 84*701da286SLi Liu remote-endpoint = <&mdss_dsi0_in>; 85*701da286SLi Liu }; 86*701da286SLi Liu }; 87*701da286SLi Liu }; 88*701da286SLi Liu 89*701da286SLi Liu mdp_opp_table: opp-table { 90*701da286SLi Liu compatible = "operating-points-v2"; 91*701da286SLi Liu 92*701da286SLi Liu opp-19200000 { 93*701da286SLi Liu opp-hz = /bits/ 64 <19200000>; 94*701da286SLi Liu required-opps = <&rpmhpd_opp_low_svs>; 95*701da286SLi Liu }; 96*701da286SLi Liu 97*701da286SLi Liu opp-25600000 { 98*701da286SLi Liu opp-hz = /bits/ 64 <25600000>; 99*701da286SLi Liu required-opps = <&rpmhpd_opp_svs>; 100*701da286SLi Liu }; 101*701da286SLi Liu 102*701da286SLi Liu opp-307200000 { 103*701da286SLi Liu opp-hz = /bits/ 64 <307200000>; 104*701da286SLi Liu required-opps = <&rpmhpd_opp_nom>; 105*701da286SLi Liu }; 106*701da286SLi Liu }; 107*701da286SLi Liu }; 108*701da286SLi Liu... 109