xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml (revision fa79e55d467366a2c52c68a261a0d6ea5f8a6534) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SA87755P Display MDSS
8
9maintainers:
10  - Mahadevan <quic_mahap@quicinc.com>
11
12description:
13  SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DP interfaces and EDP etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sa8775p-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    maxItems: 3
33
34  interconnect-names:
35    maxItems: 3
36
37patternProperties:
38  "^display-controller@[0-9a-f]+$":
39    type: object
40    additionalProperties: true
41
42    properties:
43      compatible:
44        const: qcom,sa8775p-dpu
45
46  "^displayport-controller@[0-9a-f]+$":
47    type: object
48    additionalProperties: true
49
50    properties:
51      compatible:
52        items:
53          - const: qcom,sa8775p-dp
54
55  "^dsi@[0-9a-f]+$":
56    type: object
57    additionalProperties: true
58    properties:
59      compatible:
60        contains:
61          const: qcom,sa8775p-dsi-ctrl
62
63  "^phy@[0-9a-f]+$":
64    type: object
65    additionalProperties: true
66    properties:
67      compatible:
68        contains:
69          enum:
70            - qcom,sa8775p-dsi-phy-5nm
71            - qcom,sa8775p-edp-phy
72
73required:
74  - compatible
75
76unevaluatedProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interconnect/qcom,icc.h>
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
83    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
84    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
85    #include <dt-bindings/power/qcom,rpmhpd.h>
86    #include <dt-bindings/power/qcom-rpmpd.h>
87
88    display-subsystem@ae00000 {
89        compatible = "qcom,sa8775p-mdss";
90        reg = <0x0ae00000 0x1000>;
91        reg-names = "mdss";
92
93        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
94                        <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
95                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
96        interconnect-names = "mdp0-mem",
97                             "mdp1-mem",
98                             "cpu-cfg";
99
100        resets = <&dispcc_core_bcr>;
101        power-domains = <&dispcc_gdsc>;
102
103        clocks = <&dispcc_ahb_clk>,
104                 <&gcc GCC_DISP_HF_AXI_CLK>,
105                 <&dispcc_mdp_clk>;
106
107        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
108        interrupt-controller;
109        #interrupt-cells = <1>;
110
111        iommus = <&apps_smmu 0x1000 0x402>;
112
113        #address-cells = <1>;
114        #size-cells = <1>;
115        ranges;
116
117        display-controller@ae01000 {
118            compatible = "qcom,sa8775p-dpu";
119            reg = <0x0ae01000 0x8f000>,
120                  <0x0aeb0000 0x2008>;
121            reg-names = "mdp", "vbif";
122
123            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
124                     <&dispcc_ahb_clk>,
125                     <&dispcc_mdp_lut_clk>,
126                     <&dispcc_mdp_clk>,
127                     <&dispcc_mdp_vsync_clk>;
128            clock-names = "nrt_bus",
129                          "iface",
130                          "lut",
131                          "core",
132                          "vsync";
133
134            assigned-clocks = <&dispcc_mdp_vsync_clk>;
135            assigned-clock-rates = <19200000>;
136
137            operating-points-v2 = <&mdss0_mdp_opp_table>;
138            power-domains = <&rpmhpd RPMHPD_MMCX>;
139
140            interrupt-parent = <&mdss0>;
141            interrupts = <0>;
142
143            ports {
144                #address-cells = <1>;
145                #size-cells = <0>;
146
147                port@0 {
148                    reg = <0>;
149                    dpu_intf0_out: endpoint {
150                        remote-endpoint = <&mdss0_dp0_in>;
151                    };
152                };
153
154                port@1 {
155                    reg = <1>;
156                    dpu_intf1_out: endpoint {
157                        remote-endpoint = <&mdss0_dsi0_in>;
158                    };
159                };
160
161                port@2 {
162                    reg = <2>;
163                    dpu_intf2_out: endpoint {
164                        remote-endpoint = <&mdss0_dsi1_in>;
165                    };
166                };
167            };
168
169            mdss0_mdp_opp_table: opp-table {
170                compatible = "operating-points-v2";
171
172                opp-375000000 {
173                    opp-hz = /bits/ 64 <375000000>;
174                    required-opps = <&rpmhpd_opp_svs_l1>;
175                };
176
177                opp-500000000 {
178                    opp-hz = /bits/ 64 <500000000>;
179                    required-opps = <&rpmhpd_opp_nom>;
180                };
181
182                opp-575000000 {
183                    opp-hz = /bits/ 64 <575000000>;
184                    required-opps = <&rpmhpd_opp_turbo>;
185                };
186
187                opp-650000000 {
188                    opp-hz = /bits/ 64 <650000000>;
189                    required-opps = <&rpmhpd_opp_turbo_l1>;
190                };
191            };
192        };
193
194        mdss0_dp0_phy: phy@aec2a00 {
195            compatible = "qcom,sa8775p-edp-phy";
196
197            reg = <0x0aec2a00 0x200>,
198                  <0x0aec2200 0xd0>,
199                  <0x0aec2600 0xd0>,
200                  <0x0aec2000 0x1c8>;
201
202            clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
203                     <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
204            clock-names = "aux",
205                          "cfg_ahb";
206
207            #clock-cells = <1>;
208            #phy-cells = <0>;
209
210            vdda-phy-supply = <&vreg_l1c>;
211            vdda-pll-supply = <&vreg_l4a>;
212        };
213
214        dsi@ae94000 {
215            compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
216            reg = <0x0ae94000 0x400>;
217            reg-names = "dsi_ctrl";
218
219            interrupt-parent = <&mdss>;
220            interrupts = <4>;
221
222            clocks = <&dispc_byte_clk>,
223                     <&dispcc_intf_clk>,
224                     <&dispcc_pclk>,
225                     <&dispcc_esc_clk>,
226                     <&dispcc_ahb_clk>,
227                     <&gcc_bus_clk>;
228            clock-names = "byte",
229                          "byte_intf",
230                          "pixel",
231                          "core",
232                          "iface",
233                          "bus";
234            assigned-clocks = <&dispcc_byte_clk>,
235                              <&dispcc_pclk>;
236            assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>;
237            phys = <&mdss0_dsi0_phy>;
238
239            operating-points-v2 = <&dsi0_opp_table>;
240            power-domains = <&rpmhpd SA8775P_MMCX>;
241
242            #address-cells = <1>;
243            #size-cells = <0>;
244
245            ports {
246                #address-cells = <1>;
247                #size-cells = <0>;
248
249                port@0 {
250                    reg = <0>;
251                    mdss0_dsi0_in: endpoint {
252                        remote-endpoint = <&dpu_intf1_out>;
253                    };
254                };
255
256                port@1 {
257                    reg = <1>;
258                    mdss0_dsi0_out: endpoint { };
259                };
260            };
261
262            dsi0_opp_table: opp-table {
263                compatible = "operating-points-v2";
264
265                opp-358000000 {
266                    opp-hz = /bits/ 64 <358000000>;
267                    required-opps = <&rpmhpd_opp_svs_l1>;
268                };
269            };
270        };
271
272        mdss0_dsi0_phy: phy@ae94400 {
273            compatible = "qcom,sa8775p-dsi-phy-5nm";
274            reg = <0x0ae94400 0x200>,
275                  <0x0ae94600 0x280>,
276                  <0x0ae94900 0x27c>;
277            reg-names = "dsi_phy",
278                        "dsi_phy_lane",
279                        "dsi_pll";
280
281            #clock-cells = <1>;
282            #phy-cells = <0>;
283
284            clocks = <&dispcc_iface_clk>,
285                     <&rpmhcc_ref_clk>;
286            clock-names = "iface", "ref";
287
288            vdds-supply = <&vreg_dsi_supply>;
289        };
290
291        dsi@ae96000 {
292            compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
293            reg = <0x0ae96000 0x400>;
294            reg-names = "dsi_ctrl";
295
296            interrupt-parent = <&mdss>;
297            interrupts = <4>;
298
299            clocks = <&dispc_byte_clk>,
300                     <&dispcc_intf_clk>,
301                     <&dispcc_pclk>,
302                     <&dispcc_esc_clk>,
303                     <&dispcc_ahb_clk>,
304                     <&gcc_bus_clk>;
305            clock-names = "byte",
306                          "byte_intf",
307                          "pixel",
308                          "core",
309                          "iface",
310                          "bus";
311            assigned-clocks = <&dispcc_byte_clk>,
312                              <&dispcc_pclk>;
313            assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>;
314            phys = <&mdss0_dsi1_phy>;
315
316            operating-points-v2 = <&dsi1_opp_table>;
317            power-domains = <&rpmhpd SA8775P_MMCX>;
318
319            #address-cells = <1>;
320            #size-cells = <0>;
321
322            ports {
323                #address-cells = <1>;
324                #size-cells = <0>;
325
326                port@0 {
327                    reg = <0>;
328                    mdss0_dsi1_in: endpoint {
329                        remote-endpoint = <&dpu_intf2_out>;
330                    };
331                };
332
333                port@1 {
334                    reg = <1>;
335                    mdss0_dsi1_out: endpoint { };
336                };
337            };
338
339            dsi1_opp_table: opp-table {
340                compatible = "operating-points-v2";
341
342                opp-358000000 {
343                    opp-hz = /bits/ 64 <358000000>;
344                    required-opps = <&rpmhpd_opp_svs_l1>;
345                };
346            };
347        };
348
349        mdss0_dsi1_phy: phy@ae96400 {
350            compatible = "qcom,sa8775p-dsi-phy-5nm";
351            reg = <0x0ae96400 0x200>,
352                  <0x0ae96600 0x280>,
353                  <0x0ae96900 0x27c>;
354            reg-names = "dsi_phy",
355                        "dsi_phy_lane",
356                        "dsi_pll";
357
358            #clock-cells = <1>;
359            #phy-cells = <0>;
360
361            clocks = <&dispcc_iface_clk>,
362                     <&rpmhcc_ref_clk>;
363            clock-names = "iface", "ref";
364
365            vdds-supply = <&vreg_dsi_supply>;
366        };
367
368        displayport-controller@af54000 {
369            compatible = "qcom,sa8775p-dp";
370
371            pinctrl-0 = <&dp_hot_plug_det>;
372            pinctrl-names = "default";
373
374            reg = <0xaf54000 0x104>,
375                  <0xaf54200 0x0c0>,
376                  <0xaf55000 0x770>,
377                  <0xaf56000 0x09c>,
378                  <0xaf57000 0x09c>;
379
380            interrupt-parent = <&mdss0>;
381            interrupts = <12>;
382
383            clocks = <&dispcc_mdss_ahb_clk>,
384                     <&dispcc_dptx0_aux_clk>,
385                     <&dispcc_dptx0_link_clk>,
386                     <&dispcc_dptx0_link_intf_clk>,
387                     <&dispcc_dptx0_pixel0_clk>;
388            clock-names = "core_iface",
389                          "core_aux",
390                          "ctrl_link",
391                          "ctrl_link_iface",
392                          "stream_pixel";
393
394            assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
395                              <&dispcc_mdss_dptx0_pixel0_clk_src>;
396            assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
397
398            phys = <&mdss0_dp0_phy>;
399            phy-names = "dp";
400
401            operating-points-v2 = <&dp_opp_table>;
402            power-domains = <&rpmhpd SA8775P_MMCX>;
403
404            #sound-dai-cells = <0>;
405
406            ports {
407                #address-cells = <1>;
408                #size-cells = <0>;
409
410                port@0 {
411                    reg = <0>;
412                    mdss0_dp0_in: endpoint {
413                        remote-endpoint = <&dpu_intf0_out>;
414                    };
415                };
416
417                port@1 {
418                    reg = <1>;
419                    mdss0_dp_out: endpoint { };
420                };
421            };
422
423            dp_opp_table: opp-table {
424                compatible = "operating-points-v2";
425
426                opp-160000000 {
427                    opp-hz = /bits/ 64 <160000000>;
428                    required-opps = <&rpmhpd_opp_low_svs>;
429                };
430
431                opp-270000000 {
432                    opp-hz = /bits/ 64 <270000000>;
433                    required-opps = <&rpmhpd_opp_svs>;
434                };
435
436                opp-540000000 {
437                    opp-hz = /bits/ 64 <540000000>;
438                    required-opps = <&rpmhpd_opp_svs_l1>;
439                };
440
441                opp-810000000 {
442                    opp-hz = /bits/ 64 <810000000>;
443                    required-opps = <&rpmhpd_opp_nom>;
444                };
445            };
446        };
447    };
448...
449