1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SA87755P Display MDSS 8 9maintainers: 10 - Mahadevan <quic_mahap@quicinc.com> 11 12description: 13 SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 14 DPU display controller, DP interfaces and EDP etc. 15 16$ref: /schemas/display/msm/mdss-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sa8775p-mdss 21 22 clocks: 23 items: 24 - description: Display AHB 25 - description: Display hf AXI 26 - description: Display core 27 28 iommus: 29 maxItems: 1 30 31 interconnects: 32 maxItems: 3 33 34 interconnect-names: 35 maxItems: 3 36 37patternProperties: 38 "^display-controller@[0-9a-f]+$": 39 type: object 40 additionalProperties: true 41 42 properties: 43 compatible: 44 const: qcom,sa8775p-dpu 45 46 "^displayport-controller@[0-9a-f]+$": 47 type: object 48 additionalProperties: true 49 50 properties: 51 compatible: 52 items: 53 - const: qcom,sa8775p-dp 54 55 "^phy@[0-9a-f]+$": 56 type: object 57 additionalProperties: true 58 properties: 59 compatible: 60 const: qcom,sa8775p-edp-phy 61 62required: 63 - compatible 64 65unevaluatedProperties: false 66 67examples: 68 - | 69 #include <dt-bindings/interconnect/qcom,icc.h> 70 #include <dt-bindings/interrupt-controller/arm-gic.h> 71 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 72 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 73 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 74 #include <dt-bindings/power/qcom,rpmhpd.h> 75 #include <dt-bindings/power/qcom-rpmpd.h> 76 77 display-subsystem@ae00000 { 78 compatible = "qcom,sa8775p-mdss"; 79 reg = <0x0ae00000 0x1000>; 80 reg-names = "mdss"; 81 82 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, 83 <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, 84 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; 85 interconnect-names = "mdp0-mem", 86 "mdp1-mem", 87 "cpu-cfg"; 88 89 resets = <&dispcc_core_bcr>; 90 power-domains = <&dispcc_gdsc>; 91 92 clocks = <&dispcc_ahb_clk>, 93 <&gcc GCC_DISP_HF_AXI_CLK>, 94 <&dispcc_mdp_clk>; 95 96 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-controller; 98 #interrupt-cells = <1>; 99 100 iommus = <&apps_smmu 0x1000 0x402>; 101 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges; 105 106 display-controller@ae01000 { 107 compatible = "qcom,sa8775p-dpu"; 108 reg = <0x0ae01000 0x8f000>, 109 <0x0aeb0000 0x2008>; 110 reg-names = "mdp", "vbif"; 111 112 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 113 <&dispcc_ahb_clk>, 114 <&dispcc_mdp_lut_clk>, 115 <&dispcc_mdp_clk>, 116 <&dispcc_mdp_vsync_clk>; 117 clock-names = "nrt_bus", 118 "iface", 119 "lut", 120 "core", 121 "vsync"; 122 123 assigned-clocks = <&dispcc_mdp_vsync_clk>; 124 assigned-clock-rates = <19200000>; 125 126 operating-points-v2 = <&mdss0_mdp_opp_table>; 127 power-domains = <&rpmhpd RPMHPD_MMCX>; 128 129 interrupt-parent = <&mdss0>; 130 interrupts = <0>; 131 132 ports { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 port@0 { 137 reg = <0>; 138 dpu_intf0_out: endpoint { 139 remote-endpoint = <&mdss0_dp0_in>; 140 }; 141 }; 142 }; 143 144 mdss0_mdp_opp_table: opp-table { 145 compatible = "operating-points-v2"; 146 147 opp-375000000 { 148 opp-hz = /bits/ 64 <375000000>; 149 required-opps = <&rpmhpd_opp_svs_l1>; 150 }; 151 152 opp-500000000 { 153 opp-hz = /bits/ 64 <500000000>; 154 required-opps = <&rpmhpd_opp_nom>; 155 }; 156 157 opp-575000000 { 158 opp-hz = /bits/ 64 <575000000>; 159 required-opps = <&rpmhpd_opp_turbo>; 160 }; 161 162 opp-650000000 { 163 opp-hz = /bits/ 64 <650000000>; 164 required-opps = <&rpmhpd_opp_turbo_l1>; 165 }; 166 }; 167 }; 168 169 mdss0_dp0_phy: phy@aec2a00 { 170 compatible = "qcom,sa8775p-edp-phy"; 171 172 reg = <0x0aec2a00 0x200>, 173 <0x0aec2200 0xd0>, 174 <0x0aec2600 0xd0>, 175 <0x0aec2000 0x1c8>; 176 177 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 178 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 179 clock-names = "aux", 180 "cfg_ahb"; 181 182 #clock-cells = <1>; 183 #phy-cells = <0>; 184 185 vdda-phy-supply = <&vreg_l1c>; 186 vdda-pll-supply = <&vreg_l4a>; 187 }; 188 189 displayport-controller@af54000 { 190 compatible = "qcom,sa8775p-dp"; 191 192 pinctrl-0 = <&dp_hot_plug_det>; 193 pinctrl-names = "default"; 194 195 reg = <0xaf54000 0x104>, 196 <0xaf54200 0x0c0>, 197 <0xaf55000 0x770>, 198 <0xaf56000 0x09c>, 199 <0xaf57000 0x09c>; 200 201 interrupt-parent = <&mdss0>; 202 interrupts = <12>; 203 204 clocks = <&dispcc_mdss_ahb_clk>, 205 <&dispcc_dptx0_aux_clk>, 206 <&dispcc_dptx0_link_clk>, 207 <&dispcc_dptx0_link_intf_clk>, 208 <&dispcc_dptx0_pixel0_clk>; 209 clock-names = "core_iface", 210 "core_aux", 211 "ctrl_link", 212 "ctrl_link_iface", 213 "stream_pixel"; 214 215 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 216 <&dispcc_mdss_dptx0_pixel0_clk_src>; 217 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; 218 219 phys = <&mdss0_dp0_phy>; 220 phy-names = "dp"; 221 222 operating-points-v2 = <&dp_opp_table>; 223 power-domains = <&rpmhpd SA8775P_MMCX>; 224 225 #sound-dai-cells = <0>; 226 227 ports { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 port@0 { 232 reg = <0>; 233 mdss0_dp0_in: endpoint { 234 remote-endpoint = <&dpu_intf0_out>; 235 }; 236 }; 237 238 port@1 { 239 reg = <1>; 240 mdss0_dp_out: endpoint { }; 241 }; 242 }; 243 244 dp_opp_table: opp-table { 245 compatible = "operating-points-v2"; 246 247 opp-160000000 { 248 opp-hz = /bits/ 64 <160000000>; 249 required-opps = <&rpmhpd_opp_low_svs>; 250 }; 251 252 opp-270000000 { 253 opp-hz = /bits/ 64 <270000000>; 254 required-opps = <&rpmhpd_opp_svs>; 255 }; 256 257 opp-540000000 { 258 opp-hz = /bits/ 64 <540000000>; 259 required-opps = <&rpmhpd_opp_svs_l1>; 260 }; 261 262 opp-810000000 { 263 opp-hz = /bits/ 64 <810000000>; 264 required-opps = <&rpmhpd_opp_nom>; 265 }; 266 }; 267 }; 268 }; 269... 270