xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC8180X Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC8180X target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sc8180x-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display hf axi clock
28      - description: Display sf axi clock
29      - description: Display core clock
30
31  clock-names:
32    items:
33      - const: iface
34      - const: bus
35      - const: nrt_bus
36      - const: core
37
38  iommus:
39    maxItems: 1
40
41  interconnects:
42    maxItems: 3
43
44  interconnect-names:
45    maxItems: 3
46
47patternProperties:
48  "^display-controller@[0-9a-f]+$":
49    type: object
50    additionalProperties: true
51
52    properties:
53      compatible:
54        const: qcom,sc8180x-dpu
55
56  "^displayport-controller@[0-9a-f]+$":
57    type: object
58    additionalProperties: true
59
60    properties:
61      compatible:
62        enum:
63          - qcom,sc8180x-dp
64          - qcom,sc8180x-edp
65
66  "^dsi@[0-9a-f]+$":
67    type: object
68    additionalProperties: true
69
70    properties:
71      compatible:
72        contains:
73          const: qcom,sc8180x-dsi-ctrl
74
75  "^phy@[0-9a-f]+$":
76    type: object
77    additionalProperties: true
78
79    properties:
80      compatible:
81        const: qcom,dsi-phy-7nm
82
83unevaluatedProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
88    #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
89    #include <dt-bindings/clock/qcom,rpmh.h>
90    #include <dt-bindings/interrupt-controller/arm-gic.h>
91    #include <dt-bindings/interconnect/qcom,sc8180x.h>
92    #include <dt-bindings/power/qcom-rpmpd.h>
93
94    display-subsystem@ae00000 {
95        compatible = "qcom,sc8180x-mdss";
96        reg = <0x0ae00000 0x1000>;
97        reg-names = "mdss";
98
99        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
100                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>,
101                        <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>;
102        interconnect-names = "mdp0-mem",
103                             "mdp1-mem",
104                             "cpu-cfg";
105
106        power-domains = <&dispcc MDSS_GDSC>;
107
108        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
109                 <&gcc GCC_DISP_HF_AXI_CLK>,
110                 <&gcc GCC_DISP_SF_AXI_CLK>,
111                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112        clock-names = "iface", "bus", "nrt_bus", "core";
113
114        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
115        interrupt-controller;
116        #interrupt-cells = <1>;
117
118        iommus = <&apps_smmu 0x800 0x420>;
119
120        #address-cells = <1>;
121        #size-cells = <1>;
122        ranges;
123
124        display-controller@ae01000 {
125            compatible = "qcom,sc8180x-dpu";
126            reg = <0x0ae01000 0x8f000>,
127                  <0x0aeb0000 0x2008>;
128            reg-names = "mdp", "vbif";
129
130            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
131                     <&gcc GCC_DISP_HF_AXI_CLK>,
132                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
133                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
134                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
135                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
136            clock-names = "iface",
137                          "bus",
138                          "core",
139                          "vsync",
140                          "rot",
141                          "lut";
142
143            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
144            assigned-clock-rates = <19200000>;
145
146            operating-points-v2 = <&mdp_opp_table>;
147            power-domains = <&rpmhpd SC8180X_MMCX>;
148
149            interrupt-parent = <&mdss>;
150            interrupts = <0>;
151
152            ports {
153                #address-cells = <1>;
154                #size-cells = <0>;
155
156                port@0 {
157                    reg = <0>;
158                    dpu_intf1_out: endpoint {
159                        remote-endpoint = <&dsi0_in>;
160                    };
161                };
162
163                port@1 {
164                    reg = <1>;
165                    dpu_intf2_out: endpoint {
166                        remote-endpoint = <&dsi1_in>;
167                    };
168                };
169            };
170
171            mdp_opp_table: opp-table {
172                compatible = "operating-points-v2";
173
174                opp-171428571 {
175                    opp-hz = /bits/ 64 <171428571>;
176                    required-opps = <&rpmhpd_opp_low_svs>;
177                };
178
179                opp-300000000 {
180                    opp-hz = /bits/ 64 <300000000>;
181                    required-opps = <&rpmhpd_opp_svs>;
182                };
183
184                opp-345000000 {
185                    opp-hz = /bits/ 64 <345000000>;
186                    required-opps = <&rpmhpd_opp_svs_l1>;
187                };
188
189                opp-460000000 {
190                    opp-hz = /bits/ 64 <460000000>;
191                    required-opps = <&rpmhpd_opp_nom>;
192                };
193            };
194        };
195
196        dsi@ae94000 {
197            compatible = "qcom,sc8180x-dsi-ctrl",
198                         "qcom,mdss-dsi-ctrl";
199            reg = <0x0ae94000 0x400>;
200            reg-names = "dsi_ctrl";
201
202            interrupt-parent = <&mdss>;
203            interrupts = <4>;
204
205            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
206                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
207                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
208                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
209                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
210                     <&gcc GCC_DISP_HF_AXI_CLK>;
211            clock-names = "byte",
212                          "byte_intf",
213                          "pixel",
214                          "core",
215                          "iface",
216                          "bus";
217
218            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
219                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
220            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
221
222            operating-points-v2 = <&dsi_opp_table>;
223            power-domains = <&rpmhpd SC8180X_MMCX>;
224
225            phys = <&dsi0_phy>;
226            phy-names = "dsi";
227
228            #address-cells = <1>;
229            #size-cells = <0>;
230
231            ports {
232                #address-cells = <1>;
233                #size-cells = <0>;
234
235                port@0 {
236                    reg = <0>;
237                    dsi0_in: endpoint {
238                        remote-endpoint = <&dpu_intf1_out>;
239                    };
240                };
241
242                port@1 {
243                    reg = <1>;
244                    dsi0_out: endpoint {
245                    };
246                };
247            };
248
249            dsi_opp_table: opp-table {
250                compatible = "operating-points-v2";
251
252                opp-187500000 {
253                    opp-hz = /bits/ 64 <187500000>;
254                    required-opps = <&rpmhpd_opp_low_svs>;
255                };
256
257                opp-300000000 {
258                    opp-hz = /bits/ 64 <300000000>;
259                    required-opps = <&rpmhpd_opp_svs>;
260                };
261
262                opp-358000000 {
263                    opp-hz = /bits/ 64 <358000000>;
264                    required-opps = <&rpmhpd_opp_svs_l1>;
265                };
266            };
267        };
268
269        dsi0_phy: phy@ae94400 {
270            compatible = "qcom,dsi-phy-7nm";
271            reg = <0x0ae94400 0x200>,
272                  <0x0ae94600 0x280>,
273                  <0x0ae94900 0x260>;
274            reg-names = "dsi_phy",
275                        "dsi_phy_lane",
276                        "dsi_pll";
277
278            #clock-cells = <1>;
279            #phy-cells = <0>;
280
281            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
282                     <&rpmhcc RPMH_CXO_CLK>;
283            clock-names = "iface", "ref";
284            vdds-supply = <&vreg_dsi_phy>;
285        };
286
287        dsi@ae96000 {
288            compatible = "qcom,sc8180x-dsi-ctrl",
289                         "qcom,mdss-dsi-ctrl";
290            reg = <0x0ae96000 0x400>;
291            reg-names = "dsi_ctrl";
292
293            interrupt-parent = <&mdss>;
294            interrupts = <5>;
295
296            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
297                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
298                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
299                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
300                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
301                     <&gcc GCC_DISP_HF_AXI_CLK>;
302            clock-names = "byte",
303                          "byte_intf",
304                          "pixel",
305                          "core",
306                          "iface",
307                          "bus";
308
309            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
310                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
311            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
312
313            operating-points-v2 = <&dsi_opp_table>;
314            power-domains = <&rpmhpd SC8180X_MMCX>;
315
316            phys = <&dsi1_phy>;
317            phy-names = "dsi";
318
319            #address-cells = <1>;
320            #size-cells = <0>;
321
322            ports {
323                #address-cells = <1>;
324                #size-cells = <0>;
325
326                port@0 {
327                    reg = <0>;
328                    dsi1_in: endpoint {
329                        remote-endpoint = <&dpu_intf2_out>;
330                    };
331                };
332
333                port@1 {
334                    reg = <1>;
335                    dsi1_out: endpoint {
336                    };
337                };
338            };
339        };
340
341        dsi1_phy: phy@ae96400 {
342            compatible = "qcom,dsi-phy-7nm";
343            reg = <0x0ae96400 0x200>,
344                  <0x0ae96600 0x280>,
345                  <0x0ae96900 0x260>;
346            reg-names = "dsi_phy",
347                        "dsi_phy_lane",
348                        "dsi_pll";
349
350            #clock-cells = <1>;
351            #phy-cells = <0>;
352
353            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
354                     <&rpmhcc RPMH_CXO_CLK>;
355            clock-names = "iface", "ref";
356            vdds-supply = <&vreg_dsi_phy>;
357        };
358    };
359...
360