xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml (revision 637315cb400eed1dbe721954fea437a61a2d65b2) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Milos Display MDSS
8
9maintainers:
10  - Luca Weiss <luca.weiss@fairphone.com>
11
12description:
13  Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,milos-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display core
27
28  iommus:
29    maxItems: 1
30
31  interconnects:
32    items:
33      - description: Interconnect path from mdp0 port to the data bus
34      - description: Interconnect path from CPU to the reg bus
35
36  interconnect-names:
37    items:
38      - const: mdp0-mem
39      - const: cpu-cfg
40
41patternProperties:
42  "^display-controller@[0-9a-f]+$":
43    type: object
44    additionalProperties: true
45    properties:
46      compatible:
47        const: qcom,milos-dpu
48
49  "^displayport-controller@[0-9a-f]+$":
50    type: object
51    additionalProperties: true
52    properties:
53      compatible:
54        const: qcom,milos-dp
55
56  "^dsi@[0-9a-f]+$":
57    type: object
58    additionalProperties: true
59    properties:
60      compatible:
61        contains:
62          const: qcom,milos-dsi-ctrl
63
64  "^phy@[0-9a-f]+$":
65    type: object
66    additionalProperties: true
67    properties:
68      compatible:
69        const: qcom,milos-dsi-phy-4nm
70
71required:
72  - compatible
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
79    #include <dt-bindings/clock/qcom,milos-dispcc.h>
80    #include <dt-bindings/clock/qcom,milos-gcc.h>
81    #include <dt-bindings/clock/qcom,rpmh.h>
82    #include <dt-bindings/interconnect/qcom,icc.h>
83    #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/power/qcom,rpmhpd.h>
86
87    display-subsystem@ae00000 {
88        compatible = "qcom,milos-mdss";
89        reg = <0x0ae00000 0x1000>;
90        reg-names = "mdss";
91
92        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
93
94        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
95                 <&gcc GCC_DISP_HF_AXI_CLK>,
96                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
97
98        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
99
100        interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
101                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
102                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
103                         &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
104        interconnect-names = "mdp0-mem",
105                             "cpu-cfg";
106
107        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
108
109        iommus = <&apps_smmu 0x1c00 0x2>;
110
111        interrupt-controller;
112        #interrupt-cells = <1>;
113
114        #address-cells = <1>;
115        #size-cells = <1>;
116        ranges;
117
118        display-controller@ae01000 {
119            compatible = "qcom,milos-dpu";
120            reg = <0x0ae01000 0x8f000>,
121                  <0x0aeb0000 0x3000>;
122            reg-names = "mdp",
123                        "vbif";
124
125            interrupts-extended = <&mdss 0>;
126
127            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
128                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
129                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
130                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
131                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
132            clock-names = "nrt_bus",
133                          "iface",
134                          "lut",
135                          "core",
136                          "vsync";
137
138            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
139            assigned-clock-rates = <19200000>;
140
141            operating-points-v2 = <&mdp_opp_table>;
142
143            power-domains = <&rpmhpd RPMHPD_CX>;
144
145            ports {
146                #address-cells = <1>;
147                #size-cells = <0>;
148
149                port@0 {
150                    reg = <0>;
151
152                    dpu_intf1_out: endpoint {
153                        remote-endpoint = <&mdss_dsi0_in>;
154                    };
155                };
156            };
157
158            mdp_opp_table: opp-table {
159                compatible = "operating-points-v2";
160
161                opp-200000000 {
162                    opp-hz = /bits/ 64 <200000000>;
163                    required-opps = <&rpmhpd_opp_low_svs>;
164                };
165
166                opp-342000000 {
167                    opp-hz = /bits/ 64 <342000000>;
168                    required-opps = <&rpmhpd_opp_svs>;
169                };
170
171                opp-402000000 {
172                    opp-hz = /bits/ 64 <402000000>;
173                    required-opps = <&rpmhpd_opp_svs_l1>;
174                };
175
176                opp-535000000 {
177                    opp-hz = /bits/ 64 <535000000>;
178                    required-opps = <&rpmhpd_opp_nom>;
179                };
180
181                opp-600000000 {
182                    opp-hz = /bits/ 64 <600000000>;
183                    required-opps = <&rpmhpd_opp_nom_l1>;
184                };
185
186                opp-630000000 {
187                    opp-hz = /bits/ 64 <630000000>;
188                    required-opps = <&rpmhpd_opp_turbo>;
189                };
190            };
191        };
192
193        dsi@ae94000 {
194            compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
195            reg = <0x0ae94000 0x1000>;
196            reg-names = "dsi_ctrl";
197
198            interrupts-extended = <&mdss 4>;
199
200            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
201                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
202                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
203                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
204                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
205                     <&gcc GCC_DISP_HF_AXI_CLK>;
206            clock-names = "byte",
207                          "byte_intf",
208                          "pixel",
209                          "core",
210                          "iface",
211                          "bus";
212
213            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
214                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
215            assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
216                                     <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
217
218            operating-points-v2 = <&mdss_dsi_opp_table>;
219
220            power-domains = <&rpmhpd RPMHPD_CX>;
221
222            phys = <&mdss_dsi0_phy>;
223            phy-names = "dsi";
224
225            #address-cells = <1>;
226            #size-cells = <0>;
227
228            ports {
229                #address-cells = <1>;
230                #size-cells = <0>;
231
232                port@0 {
233                    reg = <0>;
234
235                    mdss_dsi0_in: endpoint {
236                        remote-endpoint = <&dpu_intf1_out>;
237                    };
238                };
239
240                port@1 {
241                    reg = <1>;
242
243                    mdss_dsi0_out: endpoint {
244                    };
245                };
246            };
247
248            mdss_dsi_opp_table: opp-table {
249                compatible = "operating-points-v2";
250
251                opp-187500000 {
252                    opp-hz = /bits/ 64 <187500000>;
253                    required-opps = <&rpmhpd_opp_low_svs>;
254                };
255
256                opp-300000000 {
257                    opp-hz = /bits/ 64 <300000000>;
258                    required-opps = <&rpmhpd_opp_svs>;
259                };
260
261                opp-358000000 {
262                    opp-hz = /bits/ 64 <358000000>;
263                    required-opps = <&rpmhpd_opp_svs_l1>;
264                };
265            };
266        };
267
268        mdss_dsi0_phy: phy@ae95000 {
269            compatible = "qcom,milos-dsi-phy-4nm";
270            reg = <0x0ae95000 0x200>,
271                  <0x0ae95200 0x300>,
272                  <0x0ae95500 0x400>;
273            reg-names = "dsi_phy",
274                        "dsi_phy_lane",
275                        "dsi_pll";
276
277            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
278                     <&rpmhcc RPMH_CXO_CLK>;
279            clock-names = "iface",
280                          "ref";
281
282            #clock-cells = <1>;
283            #phy-cells = <0>;
284        };
285    };
286...
287