xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Kaanapali Display MDSS
8
9maintainers:
10  - Yongxing Mou <yongxing.mou@oss.qualcomm.com>
11  - Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
12
13description:
14  Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
15  like DPU display controller, DSI and DP interfaces etc.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,kaanapali-mdss
22
23  clocks:
24    items:
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28      - description: Display AHB SWI
29
30  iommus:
31    maxItems: 1
32
33  interconnects:
34    items:
35      - description: Interconnect path from mdp0 port to the data bus
36      - description: Interconnect path from CPU to the reg bus
37
38  interconnect-names:
39    items:
40      - const: mdp0-mem
41      - const: cpu-cfg
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    additionalProperties: true
47    properties:
48      compatible:
49        const: qcom,kaanapali-dpu
50
51  "^dsi@[0-9a-f]+$":
52    type: object
53    additionalProperties: true
54    properties:
55      compatible:
56        contains:
57          const: qcom,kaanapali-dsi-ctrl
58
59  "^phy@[0-9a-f]+$":
60    type: object
61    additionalProperties: true
62    properties:
63      compatible:
64        const: qcom,kaanapali-dsi-phy-3nm
65
66required:
67  - compatible
68
69unevaluatedProperties: false
70
71examples:
72  - |
73    #include <dt-bindings/clock/qcom,rpmh.h>
74    #include <dt-bindings/interconnect/qcom,icc.h>
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76    #include <dt-bindings/phy/phy-qcom-qmp.h>
77    #include <dt-bindings/power/qcom,rpmhpd.h>
78
79    display-subsystem@9800000 {
80        compatible = "qcom,kaanapali-mdss";
81        reg = <0x09800000 0x1000>;
82        reg-names = "mdss";
83
84        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
85
86        clocks = <&disp_cc_mdss_ahb_clk>,
87                 <&gcc_disp_hf_axi_clk>,
88                 <&disp_cc_mdss_mdp_clk>,
89                 <&disp_cc_mdss_ahb_swi_clk>;
90        resets = <&disp_cc_mdss_core_bcr>;
91
92        power-domains = <&mdss_gdsc>;
93
94        iommus = <&apps_smmu 0x800 0x2>;
95
96        interrupt-controller;
97        #interrupt-cells = <1>;
98
99        #address-cells = <1>;
100        #size-cells = <1>;
101        ranges;
102
103        display-controller@9801000 {
104            compatible = "qcom,kaanapali-dpu";
105            reg = <0x09801000 0x1c8000>,
106                  <0x09b16000 0x3000>;
107            reg-names = "mdp",
108                        "vbif";
109
110            interrupts-extended = <&mdss 0>;
111
112            clocks = <&gcc_disp_hf_axi_clk>,
113                     <&disp_cc_mdss_ahb_clk>,
114                     <&disp_cc_mdss_mdp_lut_clk>,
115                     <&disp_cc_mdss_mdp_clk>,
116                     <&disp_cc_mdss_vsync_clk>;
117            clock-names = "nrt_bus",
118                          "iface",
119                          "lut",
120                          "core",
121                          "vsync";
122
123            assigned-clocks = <&disp_cc_mdss_vsync_clk>;
124            assigned-clock-rates = <19200000>;
125
126            operating-points-v2 = <&mdp_opp_table>;
127
128            power-domains = <&rpmhpd RPMHPD_MMCX>;
129
130            ports {
131                #address-cells = <1>;
132                #size-cells = <0>;
133
134                port@0 {
135                    reg = <0>;
136
137                    dpu_intf1_out: endpoint {
138                        remote-endpoint = <&mdss_dsi0_in>;
139                    };
140                };
141
142                port@1 {
143                    reg = <1>;
144
145                    dpu_intf2_out: endpoint {
146                        remote-endpoint = <&mdss_dsi1_in>;
147                    };
148                };
149            };
150
151            mdp_opp_table: opp-table {
152                compatible = "operating-points-v2";
153
154                opp-156000000 {
155                    opp-hz = /bits/ 64 <156000000>;
156                    required-opps = <&rpmhpd_opp_low_svs_d1>;
157                };
158
159                opp-207000000 {
160                    opp-hz = /bits/ 64 <207000000>;
161                    required-opps = <&rpmhpd_opp_low_svs>;
162                };
163
164                opp-337000000 {
165                    opp-hz = /bits/ 64 <337000000>;
166                    required-opps = <&rpmhpd_opp_svs>;
167                };
168
169                opp-417000000 {
170                    opp-hz = /bits/ 64 <417000000>;
171                    required-opps = <&rpmhpd_opp_svs_l1>;
172                };
173
174                opp-532000000 {
175                    opp-hz = /bits/ 64 <532000000>;
176                    required-opps = <&rpmhpd_opp_nom>;
177                };
178
179                opp-600000000 {
180                    opp-hz = /bits/ 64 <600000000>;
181                    required-opps = <&rpmhpd_opp_nom_l1>;
182                };
183
184                opp-650000000 {
185                    opp-hz = /bits/ 64 <650000000>;
186                    required-opps = <&rpmhpd_opp_turbo>;
187                };
188            };
189        };
190
191        dsi@9ac0000 {
192            compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
193            reg = <0x09ac0000 0x1000>;
194            reg-names = "dsi_ctrl";
195
196            interrupts-extended = <&mdss 4>;
197
198            clocks = <&disp_cc_mdss_byte0_clk>,
199                     <&disp_cc_mdss_byte0_intf_clk>,
200                     <&disp_cc_mdss_pclk0_clk>,
201                     <&disp_cc_mdss_esc0_clk>,
202                     <&disp_cc_mdss_ahb_clk>,
203                     <&gcc_disp_hf_axi_clk>,
204                     <&mdss_dsi0_phy 1>,
205                     <&mdss_dsi0_phy 0>,
206                     <&disp_cc_esync0_clk>,
207                     <&disp_cc_osc_clk>,
208                     <&disp_cc_mdss_byte0_clk_src>,
209                     <&disp_cc_mdss_pclk0_clk_src>;
210            clock-names = "byte",
211                          "byte_intf",
212                          "pixel",
213                          "core",
214                          "iface",
215                          "bus",
216                          "dsi_pll_pixel",
217                          "dsi_pll_byte",
218                          "esync",
219                          "osc",
220                          "byte_src",
221                          "pixel_src";
222
223            operating-points-v2 = <&mdss_dsi_opp_table>;
224
225            power-domains = <&rpmhpd RPMHPD_MMCX>;
226
227            phys = <&mdss_dsi0_phy>;
228            phy-names = "dsi";
229
230            #address-cells = <1>;
231            #size-cells = <0>;
232
233            ports {
234                #address-cells = <1>;
235                #size-cells = <0>;
236
237                port@0 {
238                    reg = <0>;
239
240                    mdss_dsi0_in: endpoint {
241                        remote-endpoint = <&dpu_intf1_out>;
242                    };
243                };
244
245                port@1 {
246                    reg = <1>;
247
248                    mdss_dsi0_out: endpoint {
249                        remote-endpoint = <&panel0_in>;
250                        data-lanes = <0 1 2 3>;
251                    };
252                };
253            };
254
255            mdss_dsi_opp_table: opp-table {
256                compatible = "operating-points-v2";
257
258                opp-187500000 {
259                    opp-hz = /bits/ 64 <187500000>;
260                    required-opps = <&rpmhpd_opp_low_svs_d1>;
261                };
262
263                opp-250000000 {
264                    opp-hz = /bits/ 64 <250000000>;
265                    required-opps = <&rpmhpd_opp_low_svs>;
266                };
267
268                opp-312500000 {
269                    opp-hz = /bits/ 64 <312500000>;
270                    required-opps = <&rpmhpd_opp_svs>;
271                };
272
273                opp-358000000 {
274                    opp-hz = /bits/ 64 <358000000>;
275                    required-opps = <&rpmhpd_opp_svs_l1>;
276                };
277            };
278        };
279
280        mdss_dsi0_phy: phy@9ac1000 {
281            compatible = "qcom,kaanapali-dsi-phy-3nm";
282            reg = <0x09ac1000 0x1cc>,
283                  <0x09ac1200 0x80>,
284                  <0x09ac1500 0x400>;
285            reg-names = "dsi_phy",
286                        "dsi_phy_lane",
287                        "dsi_pll";
288
289            clocks = <&disp_cc_mdss_ahb_clk>,
290                     <&rpmhcc RPMH_CXO_CLK>;
291            clock-names = "iface",
292                          "ref";
293
294            #clock-cells = <1>;
295            #phy-cells = <0>;
296        };
297    };
298