xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
3%YAML 1.2
4---
5
6$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: RGMU attached to certain Adreno GPUs
10
11maintainers:
12  - Rob Clark <robin.clark@oss.qualcomm.com>
13
14description:
15  RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
16  belong to Adreno A6xx family. It is a small state machine that helps to
17  toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
18  power.
19
20properties:
21  compatible:
22    items:
23      - const: qcom,adreno-rgmu-612.0
24      - const: qcom,adreno-rgmu
25
26  reg:
27    items:
28      - description: Core RGMU registers
29
30  clocks:
31    items:
32      - description: GMU clock
33      - description: GPU CX clock
34      - description: GPU AXI clock
35      - description: GPU MEMNOC clock
36      - description: GPU SMMU vote clock
37
38  clock-names:
39    items:
40      - const: gmu
41      - const: cxo
42      - const: axi
43      - const: memnoc
44      - const: smmu_vote
45
46  power-domains:
47    items:
48      - description: CX GDSC power domain
49      - description: GX GDSC power domain
50
51  power-domain-names:
52    items:
53      - const: cx
54      - const: gx
55
56  interrupts:
57    items:
58      - description: GMU OOB interrupt
59      - description: GMU interrupt
60
61  interrupt-names:
62    items:
63      - const: oob
64      - const: gmu
65
66  operating-points-v2: true
67  opp-table:
68    type: object
69
70required:
71  - compatible
72  - reg
73  - clocks
74  - clock-names
75  - power-domains
76  - power-domain-names
77  - interrupts
78  - interrupt-names
79  - operating-points-v2
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/qcom,qcs615-gpucc.h>
86    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
87    #include <dt-bindings/interrupt-controller/arm-gic.h>
88    #include <dt-bindings/power/qcom,rpmhpd.h>
89
90    gmu@506a000 {
91        compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
92
93        reg = <0x05000000 0x90000>;
94
95        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
96                 <&gpucc GPU_CC_CXO_CLK>,
97                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
98                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
99                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
100        clock-names = "gmu",
101                      "cxo",
102                      "axi",
103                      "memnoc",
104                      "smmu_vote";
105
106        power-domains = <&gpucc CX_GDSC>,
107                        <&gpucc GX_GDSC>;
108        power-domain-names = "cx",
109                             "gx";
110
111        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
113        interrupt-names = "oob",
114                          "gmu";
115
116        operating-points-v2 = <&gmu_opp_table>;
117
118        gmu_opp_table: opp-table {
119            compatible = "operating-points-v2";
120
121            opp-200000000 {
122                opp-hz = /bits/ 64 <200000000>;
123                required-opps = <&rpmhpd_opp_low_svs>;
124            };
125        };
126    };
127