164e5d3adSHsiao Chien Sung# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 264e5d3adSHsiao Chien Sung%YAML 1.2 364e5d3adSHsiao Chien Sung--- 464e5d3adSHsiao Chien Sung$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# 564e5d3adSHsiao Chien Sung$schema: http://devicetree.org/meta-schemas/core.yaml# 664e5d3adSHsiao Chien Sung 764e5d3adSHsiao Chien Sungtitle: MediaTek Display Padding 864e5d3adSHsiao Chien Sung 964e5d3adSHsiao Chien Sungmaintainers: 1064e5d3adSHsiao Chien Sung - Chun-Kuang Hu <chunkuang.hu@kernel.org> 1164e5d3adSHsiao Chien Sung - Philipp Zabel <p.zabel@pengutronix.de> 1264e5d3adSHsiao Chien Sung 1364e5d3adSHsiao Chien Sungdescription: 1464e5d3adSHsiao Chien Sung Padding provides ability to add pixels to width and height of a layer with 1564e5d3adSHsiao Chien Sung specified colors. Due to hardware design, Mixer in VDOSYS1 requires 1664e5d3adSHsiao Chien Sung width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, 1764e5d3adSHsiao Chien Sung we need Padding to deal with odd width. 1864e5d3adSHsiao Chien Sung Please notice that even if the Padding is in bypass mode, settings in 1964e5d3adSHsiao Chien Sung register must be cleared to 0, or undefined behaviors could happen. 2064e5d3adSHsiao Chien Sung 2164e5d3adSHsiao Chien Sungproperties: 2264e5d3adSHsiao Chien Sung compatible: 23*2971de06SAngeloGioacchino Del Regno oneOf: 24*2971de06SAngeloGioacchino Del Regno - enum: 256b7e0eb6SMoudy Ho - mediatek,mt8188-disp-padding 266b7e0eb6SMoudy Ho - mediatek,mt8195-mdp3-padding 27*2971de06SAngeloGioacchino Del Regno - items: 28*2971de06SAngeloGioacchino Del Regno - const: mediatek,mt8188-mdp3-padding 29*2971de06SAngeloGioacchino Del Regno - const: mediatek,mt8195-mdp3-padding 3064e5d3adSHsiao Chien Sung 3164e5d3adSHsiao Chien Sung reg: 3264e5d3adSHsiao Chien Sung maxItems: 1 3364e5d3adSHsiao Chien Sung 3464e5d3adSHsiao Chien Sung power-domains: 3564e5d3adSHsiao Chien Sung maxItems: 1 3664e5d3adSHsiao Chien Sung 3764e5d3adSHsiao Chien Sung clocks: 3864e5d3adSHsiao Chien Sung items: 3964e5d3adSHsiao Chien Sung - description: Padding's clocks 4064e5d3adSHsiao Chien Sung 4164e5d3adSHsiao Chien Sung mediatek,gce-client-reg: 4264e5d3adSHsiao Chien Sung description: 4364e5d3adSHsiao Chien Sung GCE (Global Command Engine) is a multi-core micro processor that helps 4464e5d3adSHsiao Chien Sung its clients to execute commands without interrupting CPU. This property 4564e5d3adSHsiao Chien Sung describes GCE client's information that is composed by 4 fields. 4664e5d3adSHsiao Chien Sung 1. Phandle of the GCE (there may be several GCE processors) 4764e5d3adSHsiao Chien Sung 2. Sub-system ID defined in the dt-binding like a user ID 4864e5d3adSHsiao Chien Sung (Please refer to include/dt-bindings/gce/<chip>-gce.h) 4964e5d3adSHsiao Chien Sung 3. Offset from base address of the subsys you are at 5064e5d3adSHsiao Chien Sung 4. Size of the register the client needs 5164e5d3adSHsiao Chien Sung $ref: /schemas/types.yaml#/definitions/phandle-array 5264e5d3adSHsiao Chien Sung items: 5364e5d3adSHsiao Chien Sung items: 5464e5d3adSHsiao Chien Sung - description: Phandle of the GCE 5564e5d3adSHsiao Chien Sung - description: Subsys ID defined in the dt-binding 5664e5d3adSHsiao Chien Sung - description: Offset from base address of the subsys 5764e5d3adSHsiao Chien Sung - description: Size of register 5864e5d3adSHsiao Chien Sung maxItems: 1 5964e5d3adSHsiao Chien Sung 6064e5d3adSHsiao Chien Sungrequired: 6164e5d3adSHsiao Chien Sung - compatible 6264e5d3adSHsiao Chien Sung - reg 6364e5d3adSHsiao Chien Sung - power-domains 6464e5d3adSHsiao Chien Sung - clocks 6564e5d3adSHsiao Chien Sung - mediatek,gce-client-reg 6664e5d3adSHsiao Chien Sung 6764e5d3adSHsiao Chien SungadditionalProperties: false 6864e5d3adSHsiao Chien Sung 6964e5d3adSHsiao Chien Sungexamples: 7064e5d3adSHsiao Chien Sung - | 7164e5d3adSHsiao Chien Sung #include <dt-bindings/interrupt-controller/arm-gic.h> 7264e5d3adSHsiao Chien Sung #include <dt-bindings/clock/mediatek,mt8188-clk.h> 7364e5d3adSHsiao Chien Sung #include <dt-bindings/power/mediatek,mt8188-power.h> 7464e5d3adSHsiao Chien Sung #include <dt-bindings/gce/mt8195-gce.h> 7564e5d3adSHsiao Chien Sung 7664e5d3adSHsiao Chien Sung soc { 7764e5d3adSHsiao Chien Sung #address-cells = <2>; 7864e5d3adSHsiao Chien Sung #size-cells = <2>; 7964e5d3adSHsiao Chien Sung 8064e5d3adSHsiao Chien Sung padding0: padding@1c11d000 { 8164e5d3adSHsiao Chien Sung compatible = "mediatek,mt8188-disp-padding"; 8264e5d3adSHsiao Chien Sung reg = <0 0x1c11d000 0 0x1000>; 8364e5d3adSHsiao Chien Sung clocks = <&vdosys1 CLK_VDO1_PADDING0>; 8464e5d3adSHsiao Chien Sung power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; 8564e5d3adSHsiao Chien Sung mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; 8664e5d3adSHsiao Chien Sung }; 8764e5d3adSHsiao Chien Sung }; 88