1*4ed545e7Sjason-jh.lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4ed545e7Sjason-jh.lin%YAML 1.2 3*4ed545e7Sjason-jh.lin--- 4*4ed545e7Sjason-jh.lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml# 5*4ed545e7Sjason-jh.lin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4ed545e7Sjason-jh.lin 7*4ed545e7Sjason-jh.lintitle: Mediatek display postmask 8*4ed545e7Sjason-jh.lin 9*4ed545e7Sjason-jh.linmaintainers: 10*4ed545e7Sjason-jh.lin - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11*4ed545e7Sjason-jh.lin - Philipp Zabel <p.zabel@pengutronix.de> 12*4ed545e7Sjason-jh.lin 13*4ed545e7Sjason-jh.lindescription: | 14*4ed545e7Sjason-jh.lin Mediatek display postmask, namely POSTMASK, provides round corner pattern 15*4ed545e7Sjason-jh.lin generation. 16*4ed545e7Sjason-jh.lin POSTMASK device node must be siblings to the central MMSYS_CONFIG node. 17*4ed545e7Sjason-jh.lin For a description of the MMSYS_CONFIG binding, see 18*4ed545e7Sjason-jh.lin Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml 19*4ed545e7Sjason-jh.lin for details. 20*4ed545e7Sjason-jh.lin 21*4ed545e7Sjason-jh.linproperties: 22*4ed545e7Sjason-jh.lin compatible: 23*4ed545e7Sjason-jh.lin oneOf: 24*4ed545e7Sjason-jh.lin - items: 25*4ed545e7Sjason-jh.lin - const: mediatek,mt8192-disp-postmask 26*4ed545e7Sjason-jh.lin 27*4ed545e7Sjason-jh.lin reg: 28*4ed545e7Sjason-jh.lin maxItems: 1 29*4ed545e7Sjason-jh.lin 30*4ed545e7Sjason-jh.lin interrupts: 31*4ed545e7Sjason-jh.lin maxItems: 1 32*4ed545e7Sjason-jh.lin 33*4ed545e7Sjason-jh.lin power-domains: 34*4ed545e7Sjason-jh.lin description: A phandle and PM domain specifier as defined by bindings of 35*4ed545e7Sjason-jh.lin the power controller specified by phandle. See 36*4ed545e7Sjason-jh.lin Documentation/devicetree/bindings/power/power-domain.yaml for details. 37*4ed545e7Sjason-jh.lin 38*4ed545e7Sjason-jh.lin clocks: 39*4ed545e7Sjason-jh.lin items: 40*4ed545e7Sjason-jh.lin - description: POSTMASK Clock 41*4ed545e7Sjason-jh.lin 42*4ed545e7Sjason-jh.lin mediatek,gce-client-reg: 43*4ed545e7Sjason-jh.lin description: The register of client driver can be configured by gce with 44*4ed545e7Sjason-jh.lin 4 arguments defined in this property, such as phandle of gce, subsys id, 45*4ed545e7Sjason-jh.lin register offset and size. Each GCE subsys id is mapping to a client 46*4ed545e7Sjason-jh.lin defined in the header include/dt-bindings/gce/<chip>-gce.h. 47*4ed545e7Sjason-jh.lin $ref: /schemas/types.yaml#/definitions/phandle-array 48*4ed545e7Sjason-jh.lin maxItems: 1 49*4ed545e7Sjason-jh.lin 50*4ed545e7Sjason-jh.linrequired: 51*4ed545e7Sjason-jh.lin - compatible 52*4ed545e7Sjason-jh.lin - reg 53*4ed545e7Sjason-jh.lin - interrupts 54*4ed545e7Sjason-jh.lin - power-domains 55*4ed545e7Sjason-jh.lin - clocks 56*4ed545e7Sjason-jh.lin 57*4ed545e7Sjason-jh.linadditionalProperties: false 58*4ed545e7Sjason-jh.lin 59*4ed545e7Sjason-jh.linexamples: 60*4ed545e7Sjason-jh.lin - | 61*4ed545e7Sjason-jh.lin 62*4ed545e7Sjason-jh.lin postmask0: postmask@1400d000 { 63*4ed545e7Sjason-jh.lin compatible = "mediatek,mt8192-disp-postmask"; 64*4ed545e7Sjason-jh.lin reg = <0 0x1400d000 0 0x1000>; 65*4ed545e7Sjason-jh.lin interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; 66*4ed545e7Sjason-jh.lin power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>; 67*4ed545e7Sjason-jh.lin clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 68*4ed545e7Sjason-jh.lin mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 69*4ed545e7Sjason-jh.lin }; 70