xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml (revision 1ac731c529cd4d6adbce134754b51ff7d822b145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display postmask
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display postmask, namely POSTMASK, provides round corner pattern
15  generation.
16  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - mediatek,mt8192-disp-postmask
26      - items:
27          - enum:
28              - mediatek,mt8186-disp-postmask
29              - mediatek,mt8188-disp-postmask
30          - const: mediatek,mt8192-disp-postmask
31
32  reg:
33    maxItems: 1
34
35  interrupts:
36    maxItems: 1
37
38  power-domains:
39    description: A phandle and PM domain specifier as defined by bindings of
40      the power controller specified by phandle. See
41      Documentation/devicetree/bindings/power/power-domain.yaml for details.
42
43  clocks:
44    items:
45      - description: POSTMASK Clock
46
47  mediatek,gce-client-reg:
48    description: The register of client driver can be configured by gce with
49      4 arguments defined in this property, such as phandle of gce, subsys id,
50      register offset and size. Each GCE subsys id is mapping to a client
51      defined in the header include/dt-bindings/gce/<chip>-gce.h.
52    $ref: /schemas/types.yaml#/definitions/phandle-array
53    maxItems: 1
54
55required:
56  - compatible
57  - reg
58  - interrupts
59  - power-domains
60  - clocks
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67    #include <dt-bindings/clock/mt8192-clk.h>
68    #include <dt-bindings/power/mt8192-power.h>
69    #include <dt-bindings/gce/mt8192-gce.h>
70
71    soc {
72        #address-cells = <2>;
73        #size-cells = <2>;
74
75        postmask0: postmask@1400d000 {
76            compatible = "mediatek,mt8192-disp-postmask";
77            reg = <0 0x1400d000 0 0x1000>;
78            interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
79            power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
80            clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
81            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
82        };
83    };
84