xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml (revision 1ac731c529cd4d6adbce134754b51ff7d822b145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: mediatek display DSC controller
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  The DSC standard is a specification of the algorithms used for
15  compressing and decompressing image display streams, including
16  the specification of the syntax and semantics of the compressed
17  video bit stream. DSC is designed for real-time systems with
18  real-time compression, transmission, decompression and Display.
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - mediatek,mt8195-disp-dsc
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    maxItems: 1
31
32  clocks:
33    items:
34      - description: DSC Wrapper Clock
35
36  power-domains:
37    description: A phandle and PM domain specifier as defined by bindings of
38      the power controller specified by phandle. See
39      Documentation/devicetree/bindings/power/power-domain.yaml for details.
40
41  mediatek,gce-client-reg:
42    description:
43      The register of client driver can be configured by gce with 4 arguments
44      defined in this property, such as phandle of gce, subsys id,
45      register offset and size.
46      Each subsys id is mapping to a base address of display function blocks
47      register which is defined in the gce header
48      include/dt-bindings/gce/<chip>-gce.h.
49    $ref: /schemas/types.yaml#/definitions/phandle-array
50    maxItems: 1
51
52required:
53  - compatible
54  - reg
55  - interrupts
56  - power-domains
57  - clocks
58
59additionalProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/interrupt-controller/arm-gic.h>
64    #include <dt-bindings/clock/mt8195-clk.h>
65    #include <dt-bindings/power/mt8195-power.h>
66    #include <dt-bindings/gce/mt8195-gce.h>
67
68    soc {
69        #address-cells = <2>;
70        #size-cells = <2>;
71
72        dsc0: disp_dsc_wrap@1c009000 {
73            compatible = "mediatek,mt8195-disp-dsc";
74            reg = <0 0x1c009000 0 0x1000>;
75            interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
76            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
77            clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
78            mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
79        };
80    };
81