1*1c0ff333SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1c0ff333SLiu Ying%YAML 1.2 3*1c0ff333SLiu Ying--- 4*1c0ff333SLiu Ying$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-framegen.yaml# 5*1c0ff333SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1c0ff333SLiu Ying 7*1c0ff333SLiu Yingtitle: Freescale i.MX8qxp Display Controller Frame Generator 8*1c0ff333SLiu Ying 9*1c0ff333SLiu Yingdescription: 10*1c0ff333SLiu Ying The Frame Generator (FrameGen) module generates a programmable video timing 11*1c0ff333SLiu Ying and optionally allows to synchronize the generated video timing to external 12*1c0ff333SLiu Ying synchronization signals. 13*1c0ff333SLiu Ying 14*1c0ff333SLiu Yingmaintainers: 15*1c0ff333SLiu Ying - Liu Ying <victor.liu@nxp.com> 16*1c0ff333SLiu Ying 17*1c0ff333SLiu Yingproperties: 18*1c0ff333SLiu Ying compatible: 19*1c0ff333SLiu Ying const: fsl,imx8qxp-dc-framegen 20*1c0ff333SLiu Ying 21*1c0ff333SLiu Ying reg: 22*1c0ff333SLiu Ying maxItems: 1 23*1c0ff333SLiu Ying 24*1c0ff333SLiu Ying clocks: 25*1c0ff333SLiu Ying maxItems: 1 26*1c0ff333SLiu Ying 27*1c0ff333SLiu Ying interrupts: 28*1c0ff333SLiu Ying maxItems: 8 29*1c0ff333SLiu Ying 30*1c0ff333SLiu Ying interrupt-names: 31*1c0ff333SLiu Ying items: 32*1c0ff333SLiu Ying - const: int0 33*1c0ff333SLiu Ying - const: int1 34*1c0ff333SLiu Ying - const: int2 35*1c0ff333SLiu Ying - const: int3 36*1c0ff333SLiu Ying - const: primsync_on 37*1c0ff333SLiu Ying - const: primsync_off 38*1c0ff333SLiu Ying - const: secsync_on 39*1c0ff333SLiu Ying - const: secsync_off 40*1c0ff333SLiu Ying 41*1c0ff333SLiu Yingrequired: 42*1c0ff333SLiu Ying - compatible 43*1c0ff333SLiu Ying - reg 44*1c0ff333SLiu Ying - clocks 45*1c0ff333SLiu Ying - interrupts 46*1c0ff333SLiu Ying - interrupt-names 47*1c0ff333SLiu Ying 48*1c0ff333SLiu YingadditionalProperties: false 49*1c0ff333SLiu Ying 50*1c0ff333SLiu Yingexamples: 51*1c0ff333SLiu Ying - | 52*1c0ff333SLiu Ying #include <dt-bindings/clock/imx8-lpcg.h> 53*1c0ff333SLiu Ying #include <dt-bindings/firmware/imx/rsrc.h> 54*1c0ff333SLiu Ying 55*1c0ff333SLiu Ying framegen@5618b800 { 56*1c0ff333SLiu Ying compatible = "fsl,imx8qxp-dc-framegen"; 57*1c0ff333SLiu Ying reg = <0x5618b800 0x98>; 58*1c0ff333SLiu Ying clocks = <&dc0_disp_lpcg IMX_LPCG_CLK_0>; 59*1c0ff333SLiu Ying interrupt-parent = <&dc0_intc>; 60*1c0ff333SLiu Ying interrupts = <18>, <19>, <20>, <21>, <41>, <42>, <43>, <44>; 61*1c0ff333SLiu Ying interrupt-names = "int0", "int1", "int2", "int3", 62*1c0ff333SLiu Ying "primsync_on", "primsync_off", 63*1c0ff333SLiu Ying "secsync_on", "secsync_off"; 64*1c0ff333SLiu Ying }; 65