1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8qxp Display Controller 8 9description: | 10 The Freescale i.MX8qxp Display Controller(DC) is comprised of three main 11 components that include a blit engine for 2D graphics accelerations, display 12 controller for display output processing, as well as a command sequencer. 13 14 Display buffers Source buffers 15 (AXI read master) (AXI read master) 16 | .......... | | | | 17 +---------------------------+------------+------------------+-+-+------+ 18 | Display Controller (DC) | .......... | | | | | 19 | | | | | | | 20 | @@@@@@@@@@@ +----------+------------+------------+ | | | | 21 A | | Command | | V V | | | | | 22 X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V | 23 I | | (AXI CLK) | | | | | @@@@@@@@@@ | 24 | @@@@@@@@@@@ | | Pixel Engine | | | | | 25 | | | | (AXI CLK) | | | | | 26 | V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | | 27 A | *********** | | | | | | | Blit | | 28 H <-+->| Configure | | V V V V | | Engine | | 29 B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| | 30 | *********** | | Display | | Display | | | | | 31 | | | Engine | | Engine | | | | | 32 | | | (Disp CLK)| | (Disp CLK)| | | | | 33 | @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ | 34 I | | Common | | | | | | | 35 R <-+--| Control | | | Display | | | | 36 Q | | (AXI CLK) | | | Controller | | | | 37 | @@@@@@@@@@@ +------------------------------------+ | | 38 | | | ^ | | 39 +--------------------------+----------------+-------+---------+--------+ 40 ^ | | | | 41 | V V | V 42 Clocks & Resets Display Display Panic Destination 43 Output0 Output1 Control buffer 44 (AXI write master) 45 46maintainers: 47 - Liu Ying <victor.liu@nxp.com> 48 49properties: 50 compatible: 51 const: fsl,imx8qxp-dc 52 53 reg: 54 maxItems: 1 55 56 clocks: 57 maxItems: 1 58 59 resets: 60 maxItems: 2 61 62 reset-names: 63 items: 64 - const: axi 65 - const: cfg 66 67 power-domains: 68 maxItems: 1 69 70 "#address-cells": 71 const: 1 72 73 "#size-cells": 74 const: 1 75 76 ranges: true 77 78patternProperties: 79 "^command-sequencer@[0-9a-f]+$": 80 type: object 81 additionalProperties: true 82 83 properties: 84 compatible: 85 const: fsl,imx8qxp-dc-command-sequencer 86 87 "^display-engine@[0-9a-f]+$": 88 type: object 89 additionalProperties: true 90 91 properties: 92 compatible: 93 const: fsl,imx8qxp-dc-display-engine 94 95 "^interrupt-controller@[0-9a-f]+$": 96 type: object 97 additionalProperties: true 98 99 properties: 100 compatible: 101 const: fsl,imx8qxp-dc-intc 102 103 "^pixel-engine@[0-9a-f]+$": 104 type: object 105 additionalProperties: true 106 107 properties: 108 compatible: 109 const: fsl,imx8qxp-dc-pixel-engine 110 111 "^pmu@[0-9a-f]+$": 112 type: object 113 additionalProperties: true 114 115 properties: 116 compatible: 117 const: fsl,imx8qxp-dc-axi-performance-counter 118 119required: 120 - compatible 121 - reg 122 - clocks 123 - power-domains 124 - "#address-cells" 125 - "#size-cells" 126 - ranges 127 128additionalProperties: false 129 130examples: 131 - | 132 #include <dt-bindings/clock/imx8-lpcg.h> 133 #include <dt-bindings/firmware/imx/rsrc.h> 134 135 display-controller@56180000 { 136 compatible = "fsl,imx8qxp-dc"; 137 reg = <0x56180000 0x40000>; 138 clocks = <&dc0_lpcg IMX_LPCG_CLK_4>; 139 power-domains = <&pd IMX_SC_R_DC_0>; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges; 143 144 interrupt-controller@56180040 { 145 compatible = "fsl,imx8qxp-dc-intc"; 146 reg = <0x56180040 0x60>; 147 clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; 148 interrupt-controller; 149 interrupt-parent = <&dc0_irqsteer>; 150 #interrupt-cells = <1>; 151 interrupts = <448>, <449>, <450>, <64>, 152 <65>, <66>, <67>, <68>, 153 <69>, <70>, <193>, <194>, 154 <195>, <196>, <197>, <72>, 155 <73>, <74>, <75>, <76>, 156 <77>, <78>, <79>, <80>, 157 <81>, <199>, <200>, <201>, 158 <202>, <203>, <204>, <205>, 159 <206>, <207>, <208>, <5>, 160 <0>, <1>, <2>, <3>, 161 <4>, <82>, <83>, <84>, 162 <85>, <209>, <210>, <211>, 163 <212>; 164 interrupt-names = "store9_shdload", 165 "store9_framecomplete", 166 "store9_seqcomplete", 167 "extdst0_shdload", 168 "extdst0_framecomplete", 169 "extdst0_seqcomplete", 170 "extdst4_shdload", 171 "extdst4_framecomplete", 172 "extdst4_seqcomplete", 173 "extdst1_shdload", 174 "extdst1_framecomplete", 175 "extdst1_seqcomplete", 176 "extdst5_shdload", 177 "extdst5_framecomplete", 178 "extdst5_seqcomplete", 179 "disengcfg_shdload0", 180 "disengcfg_framecomplete0", 181 "disengcfg_seqcomplete0", 182 "framegen0_int0", 183 "framegen0_int1", 184 "framegen0_int2", 185 "framegen0_int3", 186 "sig0_shdload", 187 "sig0_valid", 188 "sig0_error", 189 "disengcfg_shdload1", 190 "disengcfg_framecomplete1", 191 "disengcfg_seqcomplete1", 192 "framegen1_int0", 193 "framegen1_int1", 194 "framegen1_int2", 195 "framegen1_int3", 196 "sig1_shdload", 197 "sig1_valid", 198 "sig1_error", 199 "reserved", 200 "cmdseq_error", 201 "comctrl_sw0", 202 "comctrl_sw1", 203 "comctrl_sw2", 204 "comctrl_sw3", 205 "framegen0_primsync_on", 206 "framegen0_primsync_off", 207 "framegen0_secsync_on", 208 "framegen0_secsync_off", 209 "framegen1_primsync_on", 210 "framegen1_primsync_off", 211 "framegen1_secsync_on", 212 "framegen1_secsync_off"; 213 }; 214 215 pixel-engine@56180800 { 216 compatible = "fsl,imx8qxp-dc-pixel-engine"; 217 reg = <0x56180800 0xac00>; 218 clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 ranges; 222 }; 223 224 display-engine@5618b400 { 225 compatible = "fsl,imx8qxp-dc-display-engine"; 226 reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>; 227 reg-names = "top", "cfg"; 228 interrupt-parent = <&dc0_intc>; 229 interrupts = <15>, <16>, <17>; 230 interrupt-names = "shdload", "framecomplete", "seqcomplete"; 231 power-domains = <&pd IMX_SC_R_DC_0_PLL_0>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 }; 236 }; 237