1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-store.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8qxp Display Controller Store Unit 8 9description: | 10 The Store unit is the interface between the internal pixel processing 11 pipeline, which is 30-bit RGB plus 8-bit Alpha, and the AXI bus for 12 destination buffer access. It is used for the destination of Blit Engines. 13 It comprises a set of built-in functions to generate a wide range of buffer 14 formats. Note, that these are exactly inverse to corresponding functions in 15 the Fetch Unit. 16 17 +------X-------------------------+ 18 | | Store Unit | 19 | V | 20 | +-------+ | 21 | | Gamma | Gamma apply | 22 | +-------+ | 23 | | | 24 | V | 25 | +-------+ | 26 | | Color | RGB to YUV | 27 | +-------+ | 28 | | | 29 | V | 30 | +-------+ | 31 | | Chroma| YUV444 to 422 | 32 | +-------+ | 33 | | | 34 | V | 35 | +-------+ | 36 | | Reduce| Bit width reduction | 37 | | | dithering | 38 | +-------+ | 39 | | | 40 | V | 41 | +-------+ | 42 | | Pack | RGBA/YUV to RAW | 43 | | Encode| or Compression | 44 | +-------+ | 45 | | | 46 | V | 47 +------X-------------------------+ 48 49maintainers: 50 - Liu Ying <victor.liu@nxp.com> 51 52properties: 53 compatible: 54 const: fsl,imx8qxp-dc-store 55 56 reg: 57 maxItems: 2 58 59 reg-names: 60 items: 61 - const: pec 62 - const: cfg 63 64 interrupts: 65 maxItems: 3 66 67 interrupt-names: 68 items: 69 - const: shdload 70 - const: framecomplete 71 - const: seqcomplete 72 73 fsl,lts: 74 $ref: /schemas/types.yaml#/definitions/phandle 75 description: 76 Optional Linear Tile Store associated with the Store Unit. 77 78required: 79 - compatible 80 - reg 81 - reg-names 82 - interrupts 83 - interrupt-names 84 85additionalProperties: false 86 87examples: 88 - | 89 store@56180940 { 90 compatible = "fsl,imx8qxp-dc-store"; 91 reg = <0x56180940 0x1c>, <0x56184000 0x5c>; 92 reg-names = "pec", "cfg"; 93 interrupt-parent = <&dc0_intc>; 94 interrupts = <0>, <1>, <2>; 95 interrupt-names = "shdload", "framecomplete", "seqcomplete"; 96 }; 97