xref: /linux/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX8qxp Display Controller Pixel Engine
8
9description:
10  All Processing Units that operate in the AXI bus clock domain. Pixel
11  pipelines have the ability to stall when a destination is busy. Implements
12  all communication to memory resources and most of the image processing
13  functions. Interconnection of Processing Units is re-configurable.
14
15maintainers:
16  - Liu Ying <victor.liu@nxp.com>
17
18properties:
19  compatible:
20    const: fsl,imx8qxp-dc-pixel-engine
21
22  reg:
23    maxItems: 1
24
25  clocks:
26    maxItems: 1
27
28  "#address-cells":
29    const: 1
30
31  "#size-cells":
32    const: 1
33
34  ranges: true
35
36patternProperties:
37  "^blit-engine@[0-9a-f]+$":
38    type: object
39    additionalProperties: true
40
41    properties:
42      compatible:
43        const: fsl,imx8qxp-dc-blit-engine
44
45  "^constframe@[0-9a-f]+$":
46    type: object
47    additionalProperties: true
48
49    properties:
50      compatible:
51        const: fsl,imx8qxp-dc-constframe
52
53  "^extdst@[0-9a-f]+$":
54    type: object
55    additionalProperties: true
56
57    properties:
58      compatible:
59        const: fsl,imx8qxp-dc-extdst
60
61  "^fetchdecode@[0-9a-f]+$":
62    type: object
63    additionalProperties: true
64
65    properties:
66      compatible:
67        const: fsl,imx8qxp-dc-fetchdecode
68
69  "^fetcheco@[0-9a-f]+$":
70    type: object
71    additionalProperties: true
72
73    properties:
74      compatible:
75        const: fsl,imx8qxp-dc-fetcheco
76
77  "^fetchlayer@[0-9a-f]+$":
78    type: object
79    additionalProperties: true
80
81    properties:
82      compatible:
83        const: fsl,imx8qxp-dc-fetchlayer
84
85  "^fetchwarp@[0-9a-f]+$":
86    type: object
87    additionalProperties: true
88
89    properties:
90      compatible:
91        const: fsl,imx8qxp-dc-fetchwarp
92
93  "^hscaler@[0-9a-f]+$":
94    type: object
95    additionalProperties: true
96
97    properties:
98      compatible:
99        const: fsl,imx8qxp-dc-hscaler
100
101  "^layerblend@[0-9a-f]+$":
102    type: object
103    additionalProperties: true
104
105    properties:
106      compatible:
107        const: fsl,imx8qxp-dc-layerblend
108
109  "^matrix@[0-9a-f]+$":
110    type: object
111    additionalProperties: true
112
113    properties:
114      compatible:
115        const: fsl,imx8qxp-dc-matrix
116
117  "^safety@[0-9a-f]+$":
118    type: object
119    additionalProperties: true
120
121    properties:
122      compatible:
123        const: fsl,imx8qxp-dc-safety
124
125  "^vscaler@[0-9a-f]+$":
126    type: object
127    additionalProperties: true
128
129    properties:
130      compatible:
131        const: fsl,imx8qxp-dc-vscaler
132
133required:
134  - compatible
135  - reg
136  - clocks
137  - "#address-cells"
138  - "#size-cells"
139  - ranges
140
141additionalProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/clock/imx8-lpcg.h>
146
147    pixel-engine@56180800 {
148        compatible = "fsl,imx8qxp-dc-pixel-engine";
149        reg = <0x56180800 0xac00>;
150        clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
151        #address-cells = <1>;
152        #size-cells = <1>;
153        ranges;
154
155        constframe@56180960 {
156            compatible = "fsl,imx8qxp-dc-constframe";
157            reg = <0x56180960 0xc>, <0x56184400 0x20>;
158            reg-names = "pec", "cfg";
159        };
160
161        extdst@56180980 {
162            compatible = "fsl,imx8qxp-dc-extdst";
163            reg = <0x56180980 0x1c>, <0x56184800 0x28>;
164            reg-names = "pec", "cfg";
165            interrupt-parent = <&dc0_intc>;
166            interrupts = <3>, <4>, <5>;
167            interrupt-names = "shdload", "framecomplete", "seqcomplete";
168        };
169
170        constframe@561809a0 {
171            compatible = "fsl,imx8qxp-dc-constframe";
172            reg = <0x561809a0 0xc>, <0x56184c00 0x20>;
173            reg-names = "pec", "cfg";
174        };
175
176        extdst@561809c0 {
177            compatible = "fsl,imx8qxp-dc-extdst";
178            reg = <0x561809c0 0x1c>, <0x56185000 0x28>;
179            reg-names = "pec", "cfg";
180            interrupt-parent = <&dc0_intc>;
181            interrupts = <6>, <7>, <8>;
182            interrupt-names = "shdload", "framecomplete", "seqcomplete";
183        };
184
185        constframe@561809e0 {
186            compatible = "fsl,imx8qxp-dc-constframe";
187            reg = <0x561809e0 0xc>, <0x56185400 0x20>;
188            reg-names = "pec", "cfg";
189        };
190
191        extdst@56180a00 {
192            compatible = "fsl,imx8qxp-dc-extdst";
193            reg = <0x56180a00 0x1c>, <0x56185800 0x28>;
194            reg-names = "pec", "cfg";
195            interrupt-parent = <&dc0_intc>;
196            interrupts = <9>, <10>, <11>;
197            interrupt-names = "shdload", "framecomplete", "seqcomplete";
198        };
199
200        constframe@56180a20 {
201            compatible = "fsl,imx8qxp-dc-constframe";
202            reg = <0x56180a20 0xc>, <0x56185c00 0x20>;
203            reg-names = "pec", "cfg";
204        };
205
206        extdst@56180a40 {
207            compatible = "fsl,imx8qxp-dc-extdst";
208            reg = <0x56180a40 0x1c>, <0x56186000 0x28>;
209            reg-names = "pec", "cfg";
210            interrupt-parent = <&dc0_intc>;
211            interrupts = <12>, <13>, <14>;
212            interrupt-names = "shdload", "framecomplete", "seqcomplete";
213        };
214
215        fetchwarp@56180a60 {
216            compatible = "fsl,imx8qxp-dc-fetchwarp";
217            reg = <0x56180a60 0x10>, <0x56186400 0x190>;
218            reg-names = "pec", "cfg";
219        };
220
221        fetchlayer@56180ac0 {
222            compatible = "fsl,imx8qxp-dc-fetchlayer";
223            reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
224            reg-names = "pec", "cfg";
225        };
226
227        layerblend@56180ba0 {
228            compatible = "fsl,imx8qxp-dc-layerblend";
229            reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
230            reg-names = "pec", "cfg";
231        };
232
233        layerblend@56180bc0 {
234            compatible = "fsl,imx8qxp-dc-layerblend";
235            reg = <0x56180bc0 0x10>, <0x5618a800 0x20>;
236            reg-names = "pec", "cfg";
237        };
238
239        layerblend@56180be0 {
240            compatible = "fsl,imx8qxp-dc-layerblend";
241            reg = <0x56180be0 0x10>, <0x5618ac00 0x20>;
242            reg-names = "pec", "cfg";
243        };
244
245        layerblend@56180c00 {
246            compatible = "fsl,imx8qxp-dc-layerblend";
247            reg = <0x56180c00 0x10>, <0x5618b000 0x20>;
248            reg-names = "pec", "cfg";
249        };
250    };
251