1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale i.MX8qxp Display Controller Command Sequencer 8 9description: | 10 The Command Sequencer is designed to autonomously process command lists. 11 By that it can load setups into the DC configuration and synchronize to 12 hardware events. This releases a system's CPU from workload, because it 13 does not need to wait for certain events. Also it simplifies SW architecture, 14 because no interrupt handlers are required. Setups are read via AXI bus, 15 while write access to configuration registers occurs directly via an internal 16 bus. This saves bandwidth for the AXI interconnect and improves the system 17 architecture in terms of safety aspects. 18 19maintainers: 20 - Liu Ying <victor.liu@nxp.com> 21 22properties: 23 compatible: 24 const: fsl,imx8qxp-dc-command-sequencer 25 26 reg: 27 maxItems: 1 28 29 clocks: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 5 34 35 interrupt-names: 36 items: 37 - const: error 38 - const: sw0 39 - const: sw1 40 - const: sw2 41 - const: sw3 42 43 sram: 44 $ref: /schemas/types.yaml#/definitions/phandle 45 description: phandle pointing to the mmio-sram device node 46 47required: 48 - compatible 49 - reg 50 - clocks 51 - interrupts 52 - interrupt-names 53 54additionalProperties: false 55 56examples: 57 - | 58 #include <dt-bindings/clock/imx8-lpcg.h> 59 60 command-sequencer@56180400 { 61 compatible = "fsl,imx8qxp-dc-command-sequencer"; 62 reg = <0x56180400 0x1a4>; 63 clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; 64 interrupt-parent = <&dc0_intc>; 65 interrupts = <36>, <37>, <38>, <39>, <40>; 66 interrupt-names = "error", "sw0", "sw1", "sw2", "sw3"; 67 }; 68