xref: /linux/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: T-Head TH1520 DesignWare HDMI TX Encoder
8
9maintainers:
10  - Icenowy Zheng <uwu@icenowy.me>
11
12description:
13  The HDMI transmitter is a Synopsys DesignWare HDMI TX controller
14  paired with a DesignWare HDMI Gen2 TX PHY.
15
16allOf:
17  - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
18
19properties:
20  compatible:
21    enum:
22      - thead,th1520-dw-hdmi
23
24  reg-io-width:
25    const: 4
26
27  clocks:
28    maxItems: 4
29
30  clock-names:
31    items:
32      - const: iahb
33      - const: isfr
34      - const: cec
35      - const: pix
36
37  resets:
38    items:
39      - description: Main reset
40      - description: Configuration APB reset
41
42  reset-names:
43    items:
44      - const: main
45      - const: apb
46
47  ports:
48    $ref: /schemas/graph.yaml#/properties/ports
49
50    properties:
51      port@0:
52        $ref: /schemas/graph.yaml#/properties/port
53        description: Input port connected to DC8200 DPU "DP" output
54
55      port@1:
56        $ref: /schemas/graph.yaml#/properties/port
57        description: HDMI output port
58
59    required:
60      - port@0
61      - port@1
62
63required:
64  - compatible
65  - reg
66  - reg-io-width
67  - clocks
68  - clock-names
69  - resets
70  - reset-names
71  - interrupts
72  - ports
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/interrupt-controller/irq.h>
79    #include <dt-bindings/clock/thead,th1520-clk-ap.h>
80    #include <dt-bindings/reset/thead,th1520-reset.h>
81
82    soc {
83      #address-cells = <2>;
84      #size-cells = <2>;
85
86      hdmi@ffef540000 {
87        compatible = "thead,th1520-dw-hdmi";
88        reg = <0xff 0xef540000 0x0 0x40000>;
89        reg-io-width = <4>;
90        interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
91        clocks = <&clk_vo CLK_HDMI_PCLK>,
92                 <&clk_vo CLK_HDMI_SFR>,
93                 <&clk_vo CLK_HDMI_CEC>,
94                 <&clk_vo CLK_HDMI_PIXCLK>;
95        clock-names = "iahb", "isfr", "cec", "pix";
96        resets = <&rst_vo TH1520_RESET_ID_HDMI>,
97                 <&rst_vo TH1520_RESET_ID_HDMI_APB>;
98        reset-names = "main", "apb";
99
100        ports {
101          #address-cells = <1>;
102          #size-cells = <0>;
103          port@0 {
104            reg = <0>;
105
106            hdmi_in: endpoint {
107              remote-endpoint = <&dpu_out_dp1>;
108            };
109          };
110
111          port@1 {
112            reg = <1>;
113
114            hdmi_out_conn: endpoint {
115              remote-endpoint = <&hdmi_conn_in>;
116            };
117          };
118        };
119      };
120    };
121