xref: /linux/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml (revision 67f8bc848ee31831336bd478e57d2f993551902e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G3L LVDS Encoder
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
12
13description: |
14  This binding describes the LVDS encoder embedded in the Renesas RZ/G3L
15  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
16  (Data) + 1 lane (Clock).
17
18properties:
19  compatible:
20    const: renesas,r9a08g046-lvds
21
22  reg:
23    maxItems: 1
24
25  clocks:
26    items:
27      - description: Peripheral clock
28      - description: PHY clock
29      - description: Dot clock
30
31  clock-names:
32    items:
33      - const: pclk
34      - const: phyclk
35      - const: dotclk
36
37  resets:
38    items:
39      - description: LVDS_RESET_N
40      - description: MIPI_DSI_PRESET_N
41      - description: MIPI_DSI_CMN_RSTB
42      - description: MIPI_DSI_ARESET_N
43
44  reset-names:
45    items:
46      - const: lvdrst
47      - const: prst
48      - const: rst
49      - const: arst
50
51  power-domains:
52    maxItems: 1
53
54  ports:
55    $ref: /schemas/graph.yaml#/properties/ports
56
57    properties:
58      port@0:
59        $ref: /schemas/graph.yaml#/properties/port
60        description: Input channel, directly connected to the Display Unit.
61
62      port@1:
63        $ref: /schemas/graph.yaml#/properties/port
64        description: |
65          Output channel, directly connected to the LVDS panel or bridge.
66
67    required:
68      - port@0
69      - port@1
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-names
76  - resets
77  - reset-names
78  - power-domains
79  - ports
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
86
87    lvds@108a0000 {
88        compatible = "renesas,r9a08g046-lvds";
89        reg = <0x108a0000 0x10000>;
90        clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
91                 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
92                 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
93        clock-names = "pclk", "phyclk", "dotclk";
94        resets = <&cpg R9A08G046_LVDS_RESET_N>,
95                 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
96                 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
97                 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
98        reset-names = "lvdrst", "prst", "rst", "arst";
99        power-domains = <&cpg>;
100
101        ports {
102            #address-cells = <1>;
103            #size-cells = <0>;
104
105            port@0 {
106                reg = <0>;
107                lvds0_in: endpoint {
108                    remote-endpoint = <&du_out_lvds0>;
109                };
110            };
111
112            port@1 {
113                reg = <1>;
114                lvds0_out: endpoint {
115                    remote-endpoint = <&panel_in>;
116                };
117            };
118        };
119    };
120...
121