1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/arm,komeda.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Arm Komeda display processor 8 9maintainers: 10 - Liviu Dudau <Liviu.Dudau@arm.com> 11 - Andre Przywara <andre.przywara@arm.com> 12 13description: 14 The Arm Mali D71 display processor supports up to two displays with up 15 to a 4K resolution each. Each pipeline can be composed of up to four 16 layers. It is typically connected to a digital display connector like HDMI. 17 18properties: 19 compatible: 20 oneOf: 21 - items: 22 - enum: 23 - arm,mali-d32 24 - armchina,linlon-d6 25 - const: arm,mali-d71 26 - const: arm,mali-d71 27 28 reg: 29 maxItems: 1 30 31 interrupts: 32 maxItems: 1 33 34 clock-names: 35 const: aclk 36 37 clocks: 38 maxItems: 1 39 description: The main DPU processor clock 40 41 "#address-cells": 42 const: 1 43 44 "#size-cells": 45 const: 0 46 47 memory-region: 48 maxItems: 1 49 description: 50 Phandle to a node describing memory to be used for the framebuffer. 51 If not present, the framebuffer may be located anywhere in memory. 52 53 iommus: 54 description: 55 The stream IDs for each of the used pipelines, each four IDs for the 56 four layers, plus one for the write-back stream. 57 minItems: 5 58 maxItems: 10 59 60patternProperties: 61 '^pipeline@[01]$': 62 type: object 63 additionalProperties: false 64 description: 65 clocks 66 67 properties: 68 reg: 69 enum: [ 0, 1 ] 70 71 clock-names: 72 const: pxclk 73 74 clocks: 75 maxItems: 1 76 description: The input reference for the pixel clock. 77 78 port: 79 $ref: /schemas/graph.yaml#/$defs/port-base 80 unevaluatedProperties: false 81 82additionalProperties: false 83 84required: 85 - "#address-cells" 86 - "#size-cells" 87 - compatible 88 - reg 89 - interrupts 90 - clock-names 91 - clocks 92 - pipeline@0 93 94examples: 95 - | 96 display@c00000 { 97 #address-cells = <1>; 98 #size-cells = <0>; 99 compatible = "arm,mali-d71"; 100 reg = <0xc00000 0x20000>; 101 interrupts = <168>; 102 clocks = <&dpu_aclk>; 103 clock-names = "aclk"; 104 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, 105 <&smmu 8>, 106 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, 107 <&smmu 9>; 108 109 dp0_pipe0: pipeline@0 { 110 clocks = <&fpgaosc2>; 111 clock-names = "pxclk"; 112 reg = <0>; 113 114 port { 115 dp0_pipe0_out: endpoint { 116 remote-endpoint = <&db_dvi0_in>; 117 }; 118 }; 119 }; 120 121 dp0_pipe1: pipeline@1 { 122 clocks = <&fpgaosc2>; 123 clock-names = "pxclk"; 124 reg = <1>; 125 126 port { 127 dp0_pipe1_out: endpoint { 128 remote-endpoint = <&db_dvi1_in>; 129 }; 130 }; 131 }; 132 }; 133... 134