1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/arm,komeda.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Arm Komeda display processor 8 9maintainers: 10 - Liviu Dudau <Liviu.Dudau@arm.com> 11 - Andre Przywara <andre.przywara@arm.com> 12 13description: 14 The Arm Mali D71 display processor supports up to two displays with up 15 to a 4K resolution each. Each pipeline can be composed of up to four 16 layers. It is typically connected to a digital display connector like HDMI. 17 18properties: 19 compatible: 20 oneOf: 21 - items: 22 - const: arm,mali-d32 23 - const: arm,mali-d71 24 - const: arm,mali-d71 25 26 reg: 27 maxItems: 1 28 29 interrupts: 30 maxItems: 1 31 32 clock-names: 33 const: aclk 34 35 clocks: 36 maxItems: 1 37 description: The main DPU processor clock 38 39 "#address-cells": 40 const: 1 41 42 "#size-cells": 43 const: 0 44 45 memory-region: 46 maxItems: 1 47 description: 48 Phandle to a node describing memory to be used for the framebuffer. 49 If not present, the framebuffer may be located anywhere in memory. 50 51 iommus: 52 description: 53 The stream IDs for each of the used pipelines, each four IDs for the 54 four layers, plus one for the write-back stream. 55 minItems: 5 56 maxItems: 10 57 58patternProperties: 59 '^pipeline@[01]$': 60 type: object 61 additionalProperties: false 62 description: 63 clocks 64 65 properties: 66 reg: 67 enum: [ 0, 1 ] 68 69 clock-names: 70 const: pxclk 71 72 clocks: 73 maxItems: 1 74 description: The input reference for the pixel clock. 75 76 port: 77 $ref: /schemas/graph.yaml#/$defs/port-base 78 unevaluatedProperties: false 79 80additionalProperties: false 81 82required: 83 - "#address-cells" 84 - "#size-cells" 85 - compatible 86 - reg 87 - interrupts 88 - clock-names 89 - clocks 90 - pipeline@0 91 92examples: 93 - | 94 display@c00000 { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 compatible = "arm,mali-d71"; 98 reg = <0xc00000 0x20000>; 99 interrupts = <168>; 100 clocks = <&dpu_aclk>; 101 clock-names = "aclk"; 102 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, 103 <&smmu 8>, 104 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, 105 <&smmu 9>; 106 107 dp0_pipe0: pipeline@0 { 108 clocks = <&fpgaosc2>; 109 clock-names = "pxclk"; 110 reg = <0>; 111 112 port { 113 dp0_pipe0_out: endpoint { 114 remote-endpoint = <&db_dvi0_in>; 115 }; 116 }; 117 }; 118 119 dp0_pipe1: pipeline@1 { 120 clocks = <&fpgaosc2>; 121 clock-names = "pxclk"; 122 reg = <1>; 123 124 port { 125 dp0_pipe1_out: endpoint { 126 remote-endpoint = <&db_dvi1_in>; 127 }; 128 }; 129 }; 130 }; 131... 132