1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs 8 9maintainers: 10 - Nicolas Frattaroli <nicolas.frattaroli@collabora.com> 11 12description: 13 MT8196 uses CPUFreq management hardware that supports dynamic voltage 14 frequency scaling (dvfs), and can support several performance domains. 15 16properties: 17 compatible: 18 const: mediatek,mt8196-cpufreq-hw 19 20 reg: 21 items: 22 - description: FDVFS control register region 23 - description: OPP tables and control for performance domain 0 24 - description: OPP tables and control for performance domain 1 25 - description: OPP tables and control for performance domain 2 26 27 "#performance-domain-cells": 28 const: 1 29 30required: 31 - compatible 32 - reg 33 - "#performance-domain-cells" 34 35additionalProperties: false 36 37examples: 38 - | 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a720"; 46 enable-method = "psci"; 47 performance-domains = <&performance 0>; 48 reg = <0x000>; 49 }; 50 51 /* ... */ 52 53 cpu6: cpu@600 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-x4"; 56 enable-method = "psci"; 57 performance-domains = <&performance 1>; 58 reg = <0x600>; 59 }; 60 61 cpu7: cpu@700 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-x925"; 64 enable-method = "psci"; 65 performance-domains = <&performance 2>; 66 reg = <0x700>; 67 }; 68 }; 69 70 /* ... */ 71 72 soc { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 76 performance: performance-controller@c2c2034 { 77 compatible = "mediatek,mt8196-cpufreq-hw"; 78 reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>, 79 <0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>; 80 #performance-domain-cells = <1>; 81 }; 82 }; 83