1*5970c1daSManivannan Sadhasivam# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5970c1daSManivannan Sadhasivam%YAML 1.2 3*5970c1daSManivannan Sadhasivam--- 4*5970c1daSManivannan Sadhasivam$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# 5*5970c1daSManivannan Sadhasivam$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5970c1daSManivannan Sadhasivam 7*5970c1daSManivannan Sadhasivamtitle: PCIe M.2 Mechanical Key E Connector 8*5970c1daSManivannan Sadhasivam 9*5970c1daSManivannan Sadhasivammaintainers: 10*5970c1daSManivannan Sadhasivam - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> 11*5970c1daSManivannan Sadhasivam 12*5970c1daSManivannan Sadhasivamdescription: 13*5970c1daSManivannan Sadhasivam A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E 14*5970c1daSManivannan Sadhasivam connector. Mechanical Key E connectors are used to connect Wireless 15*5970c1daSManivannan Sadhasivam Connectivity devices including combinations of Wi-Fi, BT, NFC to the host 16*5970c1daSManivannan Sadhasivam machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. 17*5970c1daSManivannan Sadhasivam 18*5970c1daSManivannan Sadhasivamproperties: 19*5970c1daSManivannan Sadhasivam compatible: 20*5970c1daSManivannan Sadhasivam const: pcie-m2-e-connector 21*5970c1daSManivannan Sadhasivam 22*5970c1daSManivannan Sadhasivam vpcie3v3-supply: 23*5970c1daSManivannan Sadhasivam description: A phandle to the regulator for 3.3v supply. 24*5970c1daSManivannan Sadhasivam 25*5970c1daSManivannan Sadhasivam vpcie1v8-supply: 26*5970c1daSManivannan Sadhasivam description: A phandle to the regulator for VIO 1.8v supply. 27*5970c1daSManivannan Sadhasivam 28*5970c1daSManivannan Sadhasivam i2c-parent: 29*5970c1daSManivannan Sadhasivam $ref: /schemas/types.yaml#/definitions/phandle 30*5970c1daSManivannan Sadhasivam description: I2C interface 31*5970c1daSManivannan Sadhasivam 32*5970c1daSManivannan Sadhasivam clocks: 33*5970c1daSManivannan Sadhasivam description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to 34*5970c1daSManivannan Sadhasivam the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for 35*5970c1daSManivannan Sadhasivam more details. 36*5970c1daSManivannan Sadhasivam maxItems: 1 37*5970c1daSManivannan Sadhasivam 38*5970c1daSManivannan Sadhasivam w-disable1-gpios: 39*5970c1daSManivannan Sadhasivam description: GPIO output to W_DISABLE1# signal. This signal is used by the 40*5970c1daSManivannan Sadhasivam host system to disable WiFi radio in the M.2 card. Refer, PCI Express M.2 41*5970c1daSManivannan Sadhasivam Specification r4.0, sec 3.1.12.3 for more details. 42*5970c1daSManivannan Sadhasivam maxItems: 1 43*5970c1daSManivannan Sadhasivam 44*5970c1daSManivannan Sadhasivam w-disable2-gpios: 45*5970c1daSManivannan Sadhasivam description: GPIO output to W_DISABLE2# signal. This signal is used by the 46*5970c1daSManivannan Sadhasivam host system to disable BT radio in the M.2 card. Refer, PCI Express M.2 47*5970c1daSManivannan Sadhasivam Specification r4.0, sec 3.1.12.3 for more details. 48*5970c1daSManivannan Sadhasivam maxItems: 1 49*5970c1daSManivannan Sadhasivam 50*5970c1daSManivannan Sadhasivam viocfg-gpios: 51*5970c1daSManivannan Sadhasivam description: GPIO input to IO voltage configuration (VIO_CFG) signal. The 52*5970c1daSManivannan Sadhasivam card drives this signal to indicate to the host system whether the card 53*5970c1daSManivannan Sadhasivam supports an independent IO voltage domain for sideband signals. Refer, 54*5970c1daSManivannan Sadhasivam PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details. 55*5970c1daSManivannan Sadhasivam maxItems: 1 56*5970c1daSManivannan Sadhasivam 57*5970c1daSManivannan Sadhasivam uart-wake-gpios: 58*5970c1daSManivannan Sadhasivam description: GPIO input to UART_WAKE# signal. The card asserts this signal 59*5970c1daSManivannan Sadhasivam to wake the host system and initiate UART interface communication. Refer, 60*5970c1daSManivannan Sadhasivam PCI Express M.2 Specification r4.0, sec 3.1.8.1 for more details. 61*5970c1daSManivannan Sadhasivam maxItems: 1 62*5970c1daSManivannan Sadhasivam 63*5970c1daSManivannan Sadhasivam sdio-wake-gpios: 64*5970c1daSManivannan Sadhasivam description: GPIO input to SDIO_WAKE# signal. The card asserts this signal 65*5970c1daSManivannan Sadhasivam to wake the host system and initiate SDIO interface communication. Refer, 66*5970c1daSManivannan Sadhasivam PCI Express M.2 Specification r4.0, sec 3.1.7 for more details. 67*5970c1daSManivannan Sadhasivam maxItems: 1 68*5970c1daSManivannan Sadhasivam 69*5970c1daSManivannan Sadhasivam sdio-reset-gpios: 70*5970c1daSManivannan Sadhasivam description: GPIO output to SDIO_RESET# signal. This signal is used by the 71*5970c1daSManivannan Sadhasivam host system to reset SDIO interface of the M.2 card. Refer, PCI Express 72*5970c1daSManivannan Sadhasivam M.2 Specification r4.0, sec 3.1.7 for more details. 73*5970c1daSManivannan Sadhasivam maxItems: 1 74*5970c1daSManivannan Sadhasivam 75*5970c1daSManivannan Sadhasivam vendor-porta-gpios: 76*5970c1daSManivannan Sadhasivam description: GPIO for the first vendor specific signal (VENDOR_PORTA). This 77*5970c1daSManivannan Sadhasivam signal's functionality is defined by the card manufacturer and may be 78*5970c1daSManivannan Sadhasivam used for proprietary features. Refer the card vendor's documentation for 79*5970c1daSManivannan Sadhasivam details. 80*5970c1daSManivannan Sadhasivam maxItems: 1 81*5970c1daSManivannan Sadhasivam 82*5970c1daSManivannan Sadhasivam vendor-portb-gpios: 83*5970c1daSManivannan Sadhasivam description: GPIO for the second vendor specific signal (VENDOR_PORTB). This 84*5970c1daSManivannan Sadhasivam signal's functionality is defined by the card manufacturer and may be 85*5970c1daSManivannan Sadhasivam used for proprietary features. Refer the card vendor's documentation for 86*5970c1daSManivannan Sadhasivam details. 87*5970c1daSManivannan Sadhasivam maxItems: 1 88*5970c1daSManivannan Sadhasivam 89*5970c1daSManivannan Sadhasivam vendor-portc-gpios: 90*5970c1daSManivannan Sadhasivam description: GPIO for the third vendor specific signal (VENDOR_PORTC). This 91*5970c1daSManivannan Sadhasivam signal's functionality is defined by the card manufacturer and may be 92*5970c1daSManivannan Sadhasivam used for proprietary features. Refer the card vendor's documentation for 93*5970c1daSManivannan Sadhasivam details. 94*5970c1daSManivannan Sadhasivam maxItems: 1 95*5970c1daSManivannan Sadhasivam 96*5970c1daSManivannan Sadhasivam ports: 97*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/ports 98*5970c1daSManivannan Sadhasivam description: OF graph bindings modeling the interfaces exposed on the 99*5970c1daSManivannan Sadhasivam connector. Since a single connector can have multiple interfaces, every 100*5970c1daSManivannan Sadhasivam interface has an assigned OF graph port number as described below. 101*5970c1daSManivannan Sadhasivam 102*5970c1daSManivannan Sadhasivam properties: 103*5970c1daSManivannan Sadhasivam port@0: 104*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/port 105*5970c1daSManivannan Sadhasivam description: PCIe interface for Wi-Fi 106*5970c1daSManivannan Sadhasivam 107*5970c1daSManivannan Sadhasivam port@1: 108*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/port 109*5970c1daSManivannan Sadhasivam description: SDIO interface for Wi-Fi 110*5970c1daSManivannan Sadhasivam 111*5970c1daSManivannan Sadhasivam port@2: 112*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/port 113*5970c1daSManivannan Sadhasivam description: USB 2.0 interface for BT 114*5970c1daSManivannan Sadhasivam 115*5970c1daSManivannan Sadhasivam port@3: 116*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/port 117*5970c1daSManivannan Sadhasivam description: UART interface for BT 118*5970c1daSManivannan Sadhasivam 119*5970c1daSManivannan Sadhasivam port@4: 120*5970c1daSManivannan Sadhasivam $ref: /schemas/graph.yaml#/properties/port 121*5970c1daSManivannan Sadhasivam description: PCM/I2S interface 122*5970c1daSManivannan Sadhasivam 123*5970c1daSManivannan Sadhasivam anyOf: 124*5970c1daSManivannan Sadhasivam - anyOf: 125*5970c1daSManivannan Sadhasivam - required: 126*5970c1daSManivannan Sadhasivam - port@0 127*5970c1daSManivannan Sadhasivam - required: 128*5970c1daSManivannan Sadhasivam - port@1 129*5970c1daSManivannan Sadhasivam - anyOf: 130*5970c1daSManivannan Sadhasivam - required: 131*5970c1daSManivannan Sadhasivam - port@2 132*5970c1daSManivannan Sadhasivam - required: 133*5970c1daSManivannan Sadhasivam - port@3 134*5970c1daSManivannan Sadhasivam 135*5970c1daSManivannan Sadhasivamrequired: 136*5970c1daSManivannan Sadhasivam - compatible 137*5970c1daSManivannan Sadhasivam - vpcie3v3-supply 138*5970c1daSManivannan Sadhasivam 139*5970c1daSManivannan SadhasivamadditionalProperties: false 140*5970c1daSManivannan Sadhasivam 141*5970c1daSManivannan Sadhasivamexamples: 142*5970c1daSManivannan Sadhasivam # PCI M.2 Key E connector for Wi-Fi/BT with PCIe/UART interfaces 143*5970c1daSManivannan Sadhasivam - | 144*5970c1daSManivannan Sadhasivam #include <dt-bindings/gpio/gpio.h> 145*5970c1daSManivannan Sadhasivam 146*5970c1daSManivannan Sadhasivam connector { 147*5970c1daSManivannan Sadhasivam compatible = "pcie-m2-e-connector"; 148*5970c1daSManivannan Sadhasivam vpcie3v3-supply = <&vreg_wcn_3p3>; 149*5970c1daSManivannan Sadhasivam vpcie1v8-supply = <&vreg_l15b_1p8>; 150*5970c1daSManivannan Sadhasivam i2c-parent = <&i2c0>; 151*5970c1daSManivannan Sadhasivam w-disable1-gpios = <&tlmm 115 GPIO_ACTIVE_LOW>; 152*5970c1daSManivannan Sadhasivam w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; 153*5970c1daSManivannan Sadhasivam viocfg-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; 154*5970c1daSManivannan Sadhasivam uart-wake-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 155*5970c1daSManivannan Sadhasivam sdio-wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 156*5970c1daSManivannan Sadhasivam sdio-reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>; 157*5970c1daSManivannan Sadhasivam 158*5970c1daSManivannan Sadhasivam ports { 159*5970c1daSManivannan Sadhasivam #address-cells = <1>; 160*5970c1daSManivannan Sadhasivam #size-cells = <0>; 161*5970c1daSManivannan Sadhasivam 162*5970c1daSManivannan Sadhasivam port@0 { 163*5970c1daSManivannan Sadhasivam reg = <0>; 164*5970c1daSManivannan Sadhasivam #address-cells = <1>; 165*5970c1daSManivannan Sadhasivam #size-cells = <0>; 166*5970c1daSManivannan Sadhasivam 167*5970c1daSManivannan Sadhasivam endpoint@0 { 168*5970c1daSManivannan Sadhasivam reg = <0>; 169*5970c1daSManivannan Sadhasivam remote-endpoint = <&pcie4_port0_ep>; 170*5970c1daSManivannan Sadhasivam }; 171*5970c1daSManivannan Sadhasivam }; 172*5970c1daSManivannan Sadhasivam 173*5970c1daSManivannan Sadhasivam port@3 { 174*5970c1daSManivannan Sadhasivam reg = <3>; 175*5970c1daSManivannan Sadhasivam #address-cells = <1>; 176*5970c1daSManivannan Sadhasivam #size-cells = <0>; 177*5970c1daSManivannan Sadhasivam 178*5970c1daSManivannan Sadhasivam endpoint@0 { 179*5970c1daSManivannan Sadhasivam reg = <0>; 180*5970c1daSManivannan Sadhasivam remote-endpoint = <&uart14_ep>; 181*5970c1daSManivannan Sadhasivam }; 182*5970c1daSManivannan Sadhasivam }; 183*5970c1daSManivannan Sadhasivam }; 184*5970c1daSManivannan Sadhasivam }; 185