1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: PCIe M.2 Mechanical Key E Connector 8 9maintainers: 10 - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> 11 12description: 13 A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E 14 connector. Mechanical Key E connectors are used to connect Wireless 15 Connectivity devices including combinations of Wi-Fi, BT, NFC to the host 16 machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C. 17 18properties: 19 compatible: 20 const: pcie-m2-e-connector 21 22 vpcie3v3-supply: 23 description: A phandle to the regulator for 3.3v supply. 24 25 vpcie1v8-supply: 26 description: A phandle to the regulator for VIO 1.8v supply. 27 28 i2c-parent: 29 $ref: /schemas/types.yaml#/definitions/phandle 30 description: I2C interface 31 32 clocks: 33 description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to 34 the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for 35 more details. 36 maxItems: 1 37 38 w-disable1-gpios: 39 description: GPIO output to W_DISABLE1# signal. This signal is used by the 40 host system to disable WiFi radio in the M.2 card. Refer, PCI Express M.2 41 Specification r4.0, sec 3.1.12.3 for more details. 42 maxItems: 1 43 44 w-disable2-gpios: 45 description: GPIO output to W_DISABLE2# signal. This signal is used by the 46 host system to disable BT radio in the M.2 card. Refer, PCI Express M.2 47 Specification r4.0, sec 3.1.12.3 for more details. 48 maxItems: 1 49 50 viocfg-gpios: 51 description: GPIO input to IO voltage configuration (VIO_CFG) signal. The 52 card drives this signal to indicate to the host system whether the card 53 supports an independent IO voltage domain for sideband signals. Refer, 54 PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details. 55 maxItems: 1 56 57 uart-wake-gpios: 58 description: GPIO input to UART_WAKE# signal. The card asserts this signal 59 to wake the host system and initiate UART interface communication. Refer, 60 PCI Express M.2 Specification r4.0, sec 3.1.8.1 for more details. 61 maxItems: 1 62 63 sdio-wake-gpios: 64 description: GPIO input to SDIO_WAKE# signal. The card asserts this signal 65 to wake the host system and initiate SDIO interface communication. Refer, 66 PCI Express M.2 Specification r4.0, sec 3.1.7 for more details. 67 maxItems: 1 68 69 sdio-reset-gpios: 70 description: GPIO output to SDIO_RESET# signal. This signal is used by the 71 host system to reset SDIO interface of the M.2 card. Refer, PCI Express 72 M.2 Specification r4.0, sec 3.1.7 for more details. 73 maxItems: 1 74 75 vendor-porta-gpios: 76 description: GPIO for the first vendor specific signal (VENDOR_PORTA). This 77 signal's functionality is defined by the card manufacturer and may be 78 used for proprietary features. Refer the card vendor's documentation for 79 details. 80 maxItems: 1 81 82 vendor-portb-gpios: 83 description: GPIO for the second vendor specific signal (VENDOR_PORTB). This 84 signal's functionality is defined by the card manufacturer and may be 85 used for proprietary features. Refer the card vendor's documentation for 86 details. 87 maxItems: 1 88 89 vendor-portc-gpios: 90 description: GPIO for the third vendor specific signal (VENDOR_PORTC). This 91 signal's functionality is defined by the card manufacturer and may be 92 used for proprietary features. Refer the card vendor's documentation for 93 details. 94 maxItems: 1 95 96 ports: 97 $ref: /schemas/graph.yaml#/properties/ports 98 description: OF graph bindings modeling the interfaces exposed on the 99 connector. Since a single connector can have multiple interfaces, every 100 interface has an assigned OF graph port number as described below. 101 102 properties: 103 port@0: 104 $ref: /schemas/graph.yaml#/properties/port 105 description: PCIe interface for Wi-Fi 106 107 port@1: 108 $ref: /schemas/graph.yaml#/properties/port 109 description: SDIO interface for Wi-Fi 110 111 port@2: 112 $ref: /schemas/graph.yaml#/properties/port 113 description: USB 2.0 interface for BT 114 115 port@3: 116 $ref: /schemas/graph.yaml#/properties/port 117 description: UART interface for BT 118 119 port@4: 120 $ref: /schemas/graph.yaml#/properties/port 121 description: PCM/I2S interface 122 123 anyOf: 124 - anyOf: 125 - required: 126 - port@0 127 - required: 128 - port@1 129 - anyOf: 130 - required: 131 - port@2 132 - required: 133 - port@3 134 135required: 136 - compatible 137 - vpcie3v3-supply 138 139additionalProperties: false 140 141examples: 142 # PCI M.2 Key E connector for Wi-Fi/BT with PCIe/UART interfaces 143 - | 144 #include <dt-bindings/gpio/gpio.h> 145 146 connector { 147 compatible = "pcie-m2-e-connector"; 148 vpcie3v3-supply = <&vreg_wcn_3p3>; 149 vpcie1v8-supply = <&vreg_l15b_1p8>; 150 i2c-parent = <&i2c0>; 151 w-disable1-gpios = <&tlmm 115 GPIO_ACTIVE_LOW>; 152 w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; 153 viocfg-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; 154 uart-wake-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 155 sdio-wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 156 sdio-reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>; 157 158 ports { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 port@0 { 163 reg = <0>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 endpoint@0 { 168 reg = <0>; 169 remote-endpoint = <&pcie4_port0_ep>; 170 }; 171 }; 172 173 port@3 { 174 reg = <3>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 178 endpoint@0 { 179 reg = <0>; 180 remote-endpoint = <&uart14_ep>; 181 }; 182 }; 183 }; 184 }; 185