1*d0d3f0f8SMichal Simek# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*d0d3f0f8SMichal Simek%YAML 1.2 3*d0d3f0f8SMichal Simek--- 4*d0d3f0f8SMichal Simek$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# 5*d0d3f0f8SMichal Simek$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d0d3f0f8SMichal Simek 7*d0d3f0f8SMichal Simektitle: Xilinx ZynqMP clock controller 8*d0d3f0f8SMichal Simek 9*d0d3f0f8SMichal Simekmaintainers: 10*d0d3f0f8SMichal Simek - Michal Simek <michal.simek@amd.com> 11*d0d3f0f8SMichal Simek 12*d0d3f0f8SMichal Simekdescription: 13*d0d3f0f8SMichal Simek The clock controller is a hardware block of Xilinx ZynqMP clock tree. It 14*d0d3f0f8SMichal Simek reads required input clock frequencies from the devicetree and acts as clock 15*d0d3f0f8SMichal Simek provider for all clock consumers of PS clocks. 16*d0d3f0f8SMichal Simek 17*d0d3f0f8SMichal Simekproperties: 18*d0d3f0f8SMichal Simek compatible: 19*d0d3f0f8SMichal Simek const: xlnx,zynqmp-clk 20*d0d3f0f8SMichal Simek 21*d0d3f0f8SMichal Simek "#clock-cells": 22*d0d3f0f8SMichal Simek const: 1 23*d0d3f0f8SMichal Simek 24*d0d3f0f8SMichal Simek clocks: 25*d0d3f0f8SMichal Simek description: List of clock specifiers which are external input 26*d0d3f0f8SMichal Simek clocks to the given clock controller. 27*d0d3f0f8SMichal Simek minItems: 5 28*d0d3f0f8SMichal Simek items: 29*d0d3f0f8SMichal Simek - description: PS reference clock 30*d0d3f0f8SMichal Simek - description: reference clock for video system 31*d0d3f0f8SMichal Simek - description: alternative PS reference clock 32*d0d3f0f8SMichal Simek - description: auxiliary reference clock 33*d0d3f0f8SMichal Simek - description: transceiver reference clock 34*d0d3f0f8SMichal Simek - description: (E)MIO clock source 35*d0d3f0f8SMichal Simek - description: GEM emio clock 36*d0d3f0f8SMichal Simek - description: Watchdog external clock 37*d0d3f0f8SMichal Simek 38*d0d3f0f8SMichal Simek clock-names: 39*d0d3f0f8SMichal Simek minItems: 5 40*d0d3f0f8SMichal Simek items: 41*d0d3f0f8SMichal Simek - const: pss_ref_clk 42*d0d3f0f8SMichal Simek - const: video_clk 43*d0d3f0f8SMichal Simek - const: pss_alt_ref_clk 44*d0d3f0f8SMichal Simek - const: aux_ref_clk 45*d0d3f0f8SMichal Simek - const: gt_crx_ref_clk 46*d0d3f0f8SMichal Simek - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" 47*d0d3f0f8SMichal Simek - pattern: "gem[0-3]+_emio_clk.*$" 48*d0d3f0f8SMichal Simek - pattern: "swdt[0-1]+_ext_clk.*$" 49*d0d3f0f8SMichal Simek 50*d0d3f0f8SMichal Simekrequired: 51*d0d3f0f8SMichal Simek - compatible 52*d0d3f0f8SMichal Simek - "#clock-cells" 53*d0d3f0f8SMichal Simek - clocks 54*d0d3f0f8SMichal Simek - clock-names 55*d0d3f0f8SMichal Simek 56*d0d3f0f8SMichal SimekadditionalProperties: false 57*d0d3f0f8SMichal Simek 58*d0d3f0f8SMichal Simekexamples: 59*d0d3f0f8SMichal Simek - | 60*d0d3f0f8SMichal Simek clock-controller { 61*d0d3f0f8SMichal Simek compatible = "xlnx,zynqmp-clk"; 62*d0d3f0f8SMichal Simek clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, 63*d0d3f0f8SMichal Simek <&aux_ref_clk>, <>_crx_ref_clk>; 64*d0d3f0f8SMichal Simek clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", 65*d0d3f0f8SMichal Simek "aux_ref_clk", "gt_crx_ref_clk"; 66*d0d3f0f8SMichal Simek #clock-cells = <1>; 67*d0d3f0f8SMichal Simek }; 68*d0d3f0f8SMichal Simek... 69