1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx ZynqMP clock controller 8 9maintainers: 10 - Michal Simek <michal.simek@amd.com> 11 12description: 13 The clock controller is a hardware block of Xilinx ZynqMP clock tree. It 14 reads required input clock frequencies from the devicetree and acts as clock 15 provider for all clock consumers of PS clocks. 16 17properties: 18 compatible: 19 const: xlnx,zynqmp-clk 20 21 "#clock-cells": 22 const: 1 23 24 clocks: 25 description: List of clock specifiers which are external input 26 clocks to the given clock controller. 27 minItems: 5 28 items: 29 - description: PS reference clock 30 - description: reference clock for video system 31 - description: alternative PS reference clock 32 - description: auxiliary reference clock 33 - description: transceiver reference clock 34 - description: (E)MIO clock source 35 - description: GEM emio clock 36 - description: Watchdog external clock 37 38 clock-names: 39 minItems: 5 40 items: 41 - const: pss_ref_clk 42 - const: video_clk 43 - const: pss_alt_ref_clk 44 - const: aux_ref_clk 45 - const: gt_crx_ref_clk 46 - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" 47 - pattern: "gem[0-3]+_emio_clk.*$" 48 - pattern: "swdt[0-1]+_ext_clk.*$" 49 50required: 51 - compatible 52 - "#clock-cells" 53 - clocks 54 - clock-names 55 56additionalProperties: false 57 58examples: 59 - | 60 clock-controller { 61 compatible = "xlnx,zynqmp-clk"; 62 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, 63 <&aux_ref_clk>, <>_crx_ref_clk>; 64 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", 65 "aux_ref_clk", "gt_crx_ref_clk"; 66 #clock-cells = <1>; 67 }; 68... 69