xref: /linux/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/ultrarisc,dp1000-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UltraRISC DP1000 Clock Controller
8
9maintainers:
10  - Jia Wang <wangjia@ultrarisc.com>
11
12description: |
13  The UltraRISC DP1000 clock controller is driven from a single external
14  oscillator input. It provides a system PLL with fractional multiplier
15  and post-divider stages, several fixed-ratio derived clocks for
16  the on-chip subsystem, Clock Configuration Register (CCR) divider
17  outputs for GMAC and the UART, I2C, and SPI root clocks, and
18  per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1.
19
20  All available clocks are defined as preprocessor macros in
21  include/dt-bindings/clock/ultrarisc,dp1000-clk.h
22
23properties:
24  compatible:
25    const: ultrarisc,dp1000-clk
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    maxItems: 1
32    description:
33      External oscillator input clock used as the parent of the PLLs.
34
35  "#clock-cells":
36    const: 1
37
38required:
39  - compatible
40  - reg
41  - clocks
42  - "#clock-cells"
43
44additionalProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/clock/ultrarisc,dp1000-clk.h>
49
50    soc {
51      #address-cells = <2>;
52      #size-cells = <2>;
53
54      clock-controller@11080000 {
55        compatible = "ultrarisc,dp1000-clk";
56        reg = <0x0 0x11080000 0x0 0x1000>;
57        clocks = <&osc>;
58        #clock-cells = <1>;
59      };
60    };
61