xref: /linux/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip RV1106 Clock and Reset Unit
8
9maintainers:
10  - Simon Glass <sjg@chromium.org>
11  - Heiko Stuebner <heiko@sntech.de>
12
13description:
14  The RV1106 clock controller generates the clock and also implements a
15  reset controller for SoC peripherals.
16
17properties:
18  compatible:
19    const: rockchip,rv1106-cru
20
21  reg:
22    maxItems: 1
23
24  "#clock-cells":
25    const: 1
26
27  "#reset-cells":
28    const: 1
29
30  clocks:
31    maxItems: 1
32
33  clock-names:
34    const: xin24m
35
36  rockchip,grf:
37    $ref: /schemas/types.yaml#/definitions/phandle
38    description:
39      Phandle to the syscon managing the "general register files" (GRF).
40      If missing, pll rates are not changeable due to the missing pll
41      lock status, and the MMC drive and sample phase clocks, whose
42      control registers live in the GRF region, are not registered.
43
44required:
45  - compatible
46  - reg
47  - "#clock-cells"
48  - "#reset-cells"
49
50additionalProperties: false
51
52examples:
53  - |
54    clock-controller@ff3b0000 {
55      compatible = "rockchip,rv1106-cru";
56      reg = <0xff3b0000 0x20000>;
57      rockchip,grf = <&grf>;
58      #clock-cells = <1>;
59      #reset-cells = <1>;
60    };
61