1*8b1750eaSTaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8b1750eaSTaniya Das%YAML 1.2 3*8b1750eaSTaniya Das--- 4*8b1750eaSTaniya Das$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml# 5*8b1750eaSTaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8b1750eaSTaniya Das 7*8b1750eaSTaniya Dastitle: Qualcomm Display Clock & Reset Controller on QCS615 8*8b1750eaSTaniya Das 9*8b1750eaSTaniya Dasmaintainers: 10*8b1750eaSTaniya Das - Taniya Das <quic_tdas@quicinc.com> 11*8b1750eaSTaniya Das 12*8b1750eaSTaniya Dasdescription: | 13*8b1750eaSTaniya Das Qualcomm display clock control module provides the clocks, resets and power 14*8b1750eaSTaniya Das domains on QCS615. 15*8b1750eaSTaniya Das 16*8b1750eaSTaniya Das See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h 17*8b1750eaSTaniya Das 18*8b1750eaSTaniya Dasproperties: 19*8b1750eaSTaniya Das compatible: 20*8b1750eaSTaniya Das const: qcom,qcs615-dispcc 21*8b1750eaSTaniya Das 22*8b1750eaSTaniya Das clocks: 23*8b1750eaSTaniya Das items: 24*8b1750eaSTaniya Das - description: Board XO source 25*8b1750eaSTaniya Das - description: GPLL0 clock source from GCC 26*8b1750eaSTaniya Das - description: Byte clock from DSI PHY0 27*8b1750eaSTaniya Das - description: Pixel clock from DSI PHY0 28*8b1750eaSTaniya Das - description: Pixel clock from DSI PHY1 29*8b1750eaSTaniya Das - description: Display port PLL link clock 30*8b1750eaSTaniya Das - description: Display port PLL VCO DIV clock 31*8b1750eaSTaniya Das 32*8b1750eaSTaniya DasallOf: 33*8b1750eaSTaniya Das - $ref: qcom,gcc.yaml# 34*8b1750eaSTaniya Das 35*8b1750eaSTaniya DasunevaluatedProperties: false 36*8b1750eaSTaniya Das 37*8b1750eaSTaniya Dasexamples: 38*8b1750eaSTaniya Das - | 39*8b1750eaSTaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 40*8b1750eaSTaniya Das #include <dt-bindings/clock/qcom,qcs615-gcc.h> 41*8b1750eaSTaniya Das clock-controller@af00000 { 42*8b1750eaSTaniya Das compatible = "qcom,qcs615-dispcc"; 43*8b1750eaSTaniya Das reg = <0x0af00000 0x20000>; 44*8b1750eaSTaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 45*8b1750eaSTaniya Das <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 46*8b1750eaSTaniya Das <&mdss_dsi0_phy 0>, 47*8b1750eaSTaniya Das <&mdss_dsi0_phy 1>, 48*8b1750eaSTaniya Das <&mdss_dsi1_phy 0>, 49*8b1750eaSTaniya Das <&mdss_dp_phy 0>, 50*8b1750eaSTaniya Das <&mdss_dp_vco 0>; 51*8b1750eaSTaniya Das #clock-cells = <1>; 52*8b1750eaSTaniya Das #reset-cells = <1>; 53*8b1750eaSTaniya Das #power-domain-cells = <1>; 54*8b1750eaSTaniya Das }; 55*8b1750eaSTaniya Das... 56