xref: /linux/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller on QCS615
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11
12description: |
13  Qualcomm display clock control module provides the clocks, resets and power
14  domains on QCS615.
15
16  See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h
17
18properties:
19  compatible:
20    const: qcom,qcs615-dispcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: GPLL0 clock source from GCC
26      - description: Byte clock from DSI PHY0
27      - description: Pixel clock from DSI PHY0
28      - description: Pixel clock from DSI PHY1
29      - description: Display port PLL link clock
30      - description: Display port PLL VCO DIV clock
31
32allOf:
33  - $ref: qcom,gcc.yaml#
34
35unevaluatedProperties: false
36
37examples:
38  - |
39    #include <dt-bindings/clock/qcom,rpmh.h>
40    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
41    clock-controller@af00000 {
42      compatible = "qcom,qcs615-dispcc";
43      reg = <0x0af00000 0x20000>;
44      clocks = <&rpmhcc RPMH_CXO_CLK>,
45               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
46               <&mdss_dsi0_phy 0>,
47               <&mdss_dsi0_phy 1>,
48               <&mdss_dsi1_phy 0>,
49               <&mdss_dp_phy 0>,
50               <&mdss_dp_vco 0>;
51      #clock-cells = <1>;
52      #reset-cells = <1>;
53      #power-domain-cells = <1>;
54    };
55...
56