1*06498d59STaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*06498d59STaniya Das%YAML 1.2 3*06498d59STaniya Das--- 4*06498d59STaniya Das$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml# 5*06498d59STaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*06498d59STaniya Das 7*06498d59STaniya Dastitle: Qualcomm Global North West and South East Clock & Reset Controller 8*06498d59STaniya Das on Nord SoC 9*06498d59STaniya Das 10*06498d59STaniya Dasmaintainers: 11*06498d59STaniya Das - Taniya Das <taniya.das@oss.qualcomm.com> 12*06498d59STaniya Das 13*06498d59STaniya Dasdescription: | 14*06498d59STaniya Das Qualcomm global clock control (NW, SE) module provides the clocks, resets 15*06498d59STaniya Das and power domains on Nord SoC. 16*06498d59STaniya Das 17*06498d59STaniya Das See also: 18*06498d59STaniya Das include/dt-bindings/clock/qcom,nord-nwgcc.h 19*06498d59STaniya Das include/dt-bindings/clock/qcom,nord-segcc.h 20*06498d59STaniya Das 21*06498d59STaniya Dasproperties: 22*06498d59STaniya Das compatible: 23*06498d59STaniya Das enum: 24*06498d59STaniya Das - qcom,nord-nwgcc 25*06498d59STaniya Das - qcom,nord-segcc 26*06498d59STaniya Das 27*06498d59STaniya Das clocks: 28*06498d59STaniya Das items: 29*06498d59STaniya Das - description: Board XO source 30*06498d59STaniya Das - description: Sleep clock source 31*06498d59STaniya Das 32*06498d59STaniya Dasrequired: 33*06498d59STaniya Das - compatible 34*06498d59STaniya Das - clocks 35*06498d59STaniya Das - '#power-domain-cells' 36*06498d59STaniya Das 37*06498d59STaniya DasallOf: 38*06498d59STaniya Das - $ref: qcom,gcc.yaml# 39*06498d59STaniya Das 40*06498d59STaniya DasunevaluatedProperties: false 41*06498d59STaniya Das 42*06498d59STaniya Dasexamples: 43*06498d59STaniya Das - | 44*06498d59STaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 45*06498d59STaniya Das clock-controller@8b00000 { 46*06498d59STaniya Das compatible = "qcom,nord-nwgcc"; 47*06498d59STaniya Das reg = <0x08b00000 0xf4200>; 48*06498d59STaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 49*06498d59STaniya Das <&sleep_clk>; 50*06498d59STaniya Das #clock-cells = <1>; 51*06498d59STaniya Das #reset-cells = <1>; 52*06498d59STaniya Das #power-domain-cells = <1>; 53*06498d59STaniya Das }; 54*06498d59STaniya Das 55*06498d59STaniya Das... 56