xref: /linux/Documentation/devicetree/bindings/clock/qcom,nord-nwgcc.yaml (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global North West and South East  Clock & Reset Controller
8       on Nord SoC
9
10maintainers:
11  - Taniya Das <taniya.das@oss.qualcomm.com>
12
13description: |
14  Qualcomm global clock control (NW, SE) module provides the clocks, resets
15  and power domains on Nord SoC.
16
17  See also:
18    include/dt-bindings/clock/qcom,nord-nwgcc.h
19    include/dt-bindings/clock/qcom,nord-segcc.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,nord-nwgcc
25      - qcom,nord-segcc
26
27  clocks:
28    items:
29      - description: Board XO source
30      - description: Sleep clock source
31
32required:
33  - compatible
34  - clocks
35  - '#power-domain-cells'
36
37allOf:
38  - $ref: qcom,gcc.yaml#
39
40unevaluatedProperties: false
41
42examples:
43  - |
44    #include <dt-bindings/clock/qcom,rpmh.h>
45    clock-controller@8b00000 {
46      compatible = "qcom,nord-nwgcc";
47      reg = <0x08b00000 0xf4200>;
48      clocks = <&rpmhcc RPMH_CXO_CLK>,
49               <&sleep_clk>;
50      #clock-cells = <1>;
51      #reset-cells = <1>;
52      #power-domain-cells = <1>;
53    };
54
55...
56