1*06498d59STaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*06498d59STaniya Das%YAML 1.2 3*06498d59STaniya Das--- 4*06498d59STaniya Das$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml# 5*06498d59STaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*06498d59STaniya Das 7*06498d59STaniya Dastitle: Qualcomm Global Clock & Reset Controller on Nord SoC 8*06498d59STaniya Das 9*06498d59STaniya Dasmaintainers: 10*06498d59STaniya Das - Taniya Das <taniya.das@oss.qualcomm.com> 11*06498d59STaniya Das 12*06498d59STaniya Dasdescription: | 13*06498d59STaniya Das Qualcomm global clock control module provides the clocks, resets and power 14*06498d59STaniya Das domains on Nord SoC. 15*06498d59STaniya Das 16*06498d59STaniya Das See also: include/dt-bindings/clock/qcom,nord-gcc.h 17*06498d59STaniya Das 18*06498d59STaniya Dasproperties: 19*06498d59STaniya Das compatible: 20*06498d59STaniya Das const: qcom,nord-gcc 21*06498d59STaniya Das 22*06498d59STaniya Das clocks: 23*06498d59STaniya Das items: 24*06498d59STaniya Das - description: Board XO source 25*06498d59STaniya Das - description: Sleep clock source 26*06498d59STaniya Das - description: PCIE A Pipe clock source 27*06498d59STaniya Das - description: PCIE B Pipe clock source 28*06498d59STaniya Das - description: PCIE C Pipe clock source 29*06498d59STaniya Das - description: PCIE D Pipe clock source 30*06498d59STaniya Das 31*06498d59STaniya Dasrequired: 32*06498d59STaniya Das - compatible 33*06498d59STaniya Das - clocks 34*06498d59STaniya Das - '#power-domain-cells' 35*06498d59STaniya Das 36*06498d59STaniya DasallOf: 37*06498d59STaniya Das - $ref: qcom,gcc.yaml# 38*06498d59STaniya Das 39*06498d59STaniya DasunevaluatedProperties: false 40*06498d59STaniya Das 41*06498d59STaniya Dasexamples: 42*06498d59STaniya Das - | 43*06498d59STaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 44*06498d59STaniya Das clock-controller@100000 { 45*06498d59STaniya Das compatible = "qcom,nord-gcc"; 46*06498d59STaniya Das reg = <0x00100000 0x1f4200>; 47*06498d59STaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 48*06498d59STaniya Das <&sleep_clk>, 49*06498d59STaniya Das <&pcie_a_pipe_clk>, 50*06498d59STaniya Das <&pcie_b_pipe_clk>, 51*06498d59STaniya Das <&pcie_c_pipe_clk>, 52*06498d59STaniya Das <&pcie_d_pipe_clk>; 53*06498d59STaniya Das #clock-cells = <1>; 54*06498d59STaniya Das #reset-cells = <1>; 55*06498d59STaniya Das #power-domain-cells = <1>; 56*06498d59STaniya Das }; 57*06498d59STaniya Das 58*06498d59STaniya Das... 59