xref: /linux/Documentation/devicetree/bindings/clock/qcom,nord-gcc.yaml (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on Nord SoC
8
9maintainers:
10  - Taniya Das <taniya.das@oss.qualcomm.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on Nord SoC.
15
16  See also: include/dt-bindings/clock/qcom,nord-gcc.h
17
18properties:
19  compatible:
20    const: qcom,nord-gcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: PCIE A Pipe clock source
27      - description: PCIE B Pipe clock source
28      - description: PCIE C Pipe clock source
29      - description: PCIE D Pipe clock source
30
31required:
32  - compatible
33  - clocks
34  - '#power-domain-cells'
35
36allOf:
37  - $ref: qcom,gcc.yaml#
38
39unevaluatedProperties: false
40
41examples:
42  - |
43    #include <dt-bindings/clock/qcom,rpmh.h>
44    clock-controller@100000 {
45      compatible = "qcom,nord-gcc";
46      reg = <0x00100000 0x1f4200>;
47      clocks = <&rpmhcc RPMH_CXO_CLK>,
48               <&sleep_clk>,
49               <&pcie_a_pipe_clk>,
50               <&pcie_b_pipe_clk>,
51               <&pcie_c_pipe_clk>,
52               <&pcie_d_pipe_clk>;
53      #clock-cells = <1>;
54      #reset-cells = <1>;
55      #power-domain-cells = <1>;
56    };
57
58...
59