xref: /linux/Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640)
1*a4937e97SLuca Weiss# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*a4937e97SLuca Weiss%YAML 1.2
3*a4937e97SLuca Weiss---
4*a4937e97SLuca Weiss$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml#
5*a4937e97SLuca Weiss$schema: http://devicetree.org/meta-schemas/core.yaml#
6*a4937e97SLuca Weiss
7*a4937e97SLuca Weisstitle: Qualcomm Video Clock & Reset Controller on Milos
8*a4937e97SLuca Weiss
9*a4937e97SLuca Weissmaintainers:
10*a4937e97SLuca Weiss  - Luca Weiss <luca.weiss@fairphone.com>
11*a4937e97SLuca Weiss
12*a4937e97SLuca Weissdescription: |
13*a4937e97SLuca Weiss  Qualcomm video clock control module provides the clocks, resets and power
14*a4937e97SLuca Weiss  domains on Milos.
15*a4937e97SLuca Weiss
16*a4937e97SLuca Weiss  See also: include/dt-bindings/clock/qcom,milos-videocc.h
17*a4937e97SLuca Weiss
18*a4937e97SLuca Weissproperties:
19*a4937e97SLuca Weiss  compatible:
20*a4937e97SLuca Weiss    const: qcom,milos-videocc
21*a4937e97SLuca Weiss
22*a4937e97SLuca Weiss  clocks:
23*a4937e97SLuca Weiss    items:
24*a4937e97SLuca Weiss      - description: Board XO source
25*a4937e97SLuca Weiss      - description: Board active XO source
26*a4937e97SLuca Weiss      - description: Sleep clock source
27*a4937e97SLuca Weiss      - description: Video AHB clock from GCC
28*a4937e97SLuca Weiss
29*a4937e97SLuca Weissrequired:
30*a4937e97SLuca Weiss  - compatible
31*a4937e97SLuca Weiss  - clocks
32*a4937e97SLuca Weiss
33*a4937e97SLuca WeissallOf:
34*a4937e97SLuca Weiss  - $ref: qcom,gcc.yaml#
35*a4937e97SLuca Weiss
36*a4937e97SLuca WeissunevaluatedProperties: false
37*a4937e97SLuca Weiss
38*a4937e97SLuca Weissexamples:
39*a4937e97SLuca Weiss  - |
40*a4937e97SLuca Weiss    #include <dt-bindings/clock/qcom,milos-gcc.h>
41*a4937e97SLuca Weiss    clock-controller@aaf0000 {
42*a4937e97SLuca Weiss        compatible = "qcom,milos-videocc";
43*a4937e97SLuca Weiss        reg = <0x0aaf0000 0x10000>;
44*a4937e97SLuca Weiss        clocks = <&bi_tcxo_div2>,
45*a4937e97SLuca Weiss                 <&bi_tcxo_ao_div2>,
46*a4937e97SLuca Weiss                 <&sleep_clk>,
47*a4937e97SLuca Weiss                 <&gcc GCC_VIDEO_AHB_CLK>;
48*a4937e97SLuca Weiss        #clock-cells = <1>;
49*a4937e97SLuca Weiss        #reset-cells = <1>;
50*a4937e97SLuca Weiss        #power-domain-cells = <1>;
51*a4937e97SLuca Weiss    };
52*a4937e97SLuca Weiss
53*a4937e97SLuca Weiss...
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