1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Global Clock & Reset Controller on Milos 8 9maintainers: 10 - Luca Weiss <luca.weiss@fairphone.com> 11 - Taniya Das <taniya.das@oss.qualcomm.com> 12 13description: | 14 Qualcomm global clock control module provides the clocks, resets and power 15 domains on Milos. 16 17 See also: 18 - include/dt-bindings/clock/qcom,eliza-gcc.h 19 - include/dt-bindings/clock/qcom,milos-gcc.h 20 21properties: 22 compatible: 23 enum: 24 - qcom,eliza-gcc 25 - qcom,milos-gcc 26 27 clocks: 28 items: 29 - description: Board XO source 30 - description: Sleep clock source 31 - description: PCIE 0 Pipe clock source 32 - description: PCIE 1 Pipe clock source 33 - description: UFS Phy Rx symbol 0 clock source 34 - description: UFS Phy Rx symbol 1 clock source 35 - description: UFS Phy Tx symbol 0 clock source 36 - description: USB3 Phy wrapper pipe clock source 37 38 power-domains: 39 items: 40 - description: CX domain 41 42required: 43 - compatible 44 - clocks 45 - power-domains 46 - '#power-domain-cells' 47 48allOf: 49 - $ref: qcom,gcc.yaml# 50 51unevaluatedProperties: false 52 53examples: 54 - | 55 #include <dt-bindings/clock/qcom,rpmh.h> 56 #include <dt-bindings/power/qcom,rpmhpd.h> 57 clock-controller@100000 { 58 compatible = "qcom,milos-gcc"; 59 reg = <0x00100000 0x1f4200>; 60 clocks = <&rpmhcc RPMH_CXO_CLK>, 61 <&sleep_clk>, 62 <&pcie0_phy>, 63 <&pcie1_phy>, 64 <&ufs_mem_phy 0>, 65 <&ufs_mem_phy 1>, 66 <&ufs_mem_phy 2>, 67 <&usb_1_qmpphy>; 68 power-domains = <&rpmhpd RPMHPD_CX>; 69 #clock-cells = <1>; 70 #reset-cells = <1>; 71 #power-domain-cells = <1>; 72 }; 73 74... 75