xref: /linux/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on Milos
8
9maintainers:
10  - Luca Weiss <luca.weiss@fairphone.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on Milos.
15
16  See also: include/dt-bindings/clock/qcom,milos-gcc.h
17
18properties:
19  compatible:
20    const: qcom,milos-gcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: PCIE 0 Pipe clock source
27      - description: PCIE 1 Pipe clock source
28      - description: UFS Phy Rx symbol 0 clock source
29      - description: UFS Phy Rx symbol 1 clock source
30      - description: UFS Phy Tx symbol 0 clock source
31      - description: USB3 Phy wrapper pipe clock source
32
33required:
34  - compatible
35  - clocks
36  - '#power-domain-cells'
37
38allOf:
39  - $ref: qcom,gcc.yaml#
40
41unevaluatedProperties: false
42
43examples:
44  - |
45    #include <dt-bindings/clock/qcom,rpmh.h>
46    clock-controller@100000 {
47        compatible = "qcom,milos-gcc";
48        reg = <0x00100000 0x1f4200>;
49        clocks = <&rpmhcc RPMH_CXO_CLK>,
50                 <&sleep_clk>,
51                 <&pcie0_phy>,
52                 <&pcie1_phy>,
53                 <&ufs_mem_phy 0>,
54                 <&ufs_mem_phy 1>,
55                 <&ufs_mem_phy 2>,
56                 <&usb_1_qmpphy>;
57        #clock-cells = <1>;
58        #reset-cells = <1>;
59        #power-domain-cells = <1>;
60    };
61
62...
63