1*95ba6820SLuca Weiss# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*95ba6820SLuca Weiss%YAML 1.2 3*95ba6820SLuca Weiss--- 4*95ba6820SLuca Weiss$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml# 5*95ba6820SLuca Weiss$schema: http://devicetree.org/meta-schemas/core.yaml# 6*95ba6820SLuca Weiss 7*95ba6820SLuca Weisstitle: Qualcomm Global Clock & Reset Controller on Milos 8*95ba6820SLuca Weiss 9*95ba6820SLuca Weissmaintainers: 10*95ba6820SLuca Weiss - Luca Weiss <luca.weiss@fairphone.com> 11*95ba6820SLuca Weiss 12*95ba6820SLuca Weissdescription: | 13*95ba6820SLuca Weiss Qualcomm global clock control module provides the clocks, resets and power 14*95ba6820SLuca Weiss domains on Milos. 15*95ba6820SLuca Weiss 16*95ba6820SLuca Weiss See also: include/dt-bindings/clock/qcom,milos-gcc.h 17*95ba6820SLuca Weiss 18*95ba6820SLuca Weissproperties: 19*95ba6820SLuca Weiss compatible: 20*95ba6820SLuca Weiss const: qcom,milos-gcc 21*95ba6820SLuca Weiss 22*95ba6820SLuca Weiss clocks: 23*95ba6820SLuca Weiss items: 24*95ba6820SLuca Weiss - description: Board XO source 25*95ba6820SLuca Weiss - description: Sleep clock source 26*95ba6820SLuca Weiss - description: PCIE 0 Pipe clock source 27*95ba6820SLuca Weiss - description: PCIE 1 Pipe clock source 28*95ba6820SLuca Weiss - description: UFS Phy Rx symbol 0 clock source 29*95ba6820SLuca Weiss - description: UFS Phy Rx symbol 1 clock source 30*95ba6820SLuca Weiss - description: UFS Phy Tx symbol 0 clock source 31*95ba6820SLuca Weiss - description: USB3 Phy wrapper pipe clock source 32*95ba6820SLuca Weiss 33*95ba6820SLuca Weissrequired: 34*95ba6820SLuca Weiss - compatible 35*95ba6820SLuca Weiss - clocks 36*95ba6820SLuca Weiss - '#power-domain-cells' 37*95ba6820SLuca Weiss 38*95ba6820SLuca WeissallOf: 39*95ba6820SLuca Weiss - $ref: qcom,gcc.yaml# 40*95ba6820SLuca Weiss 41*95ba6820SLuca WeissunevaluatedProperties: false 42*95ba6820SLuca Weiss 43*95ba6820SLuca Weissexamples: 44*95ba6820SLuca Weiss - | 45*95ba6820SLuca Weiss #include <dt-bindings/clock/qcom,rpmh.h> 46*95ba6820SLuca Weiss clock-controller@100000 { 47*95ba6820SLuca Weiss compatible = "qcom,milos-gcc"; 48*95ba6820SLuca Weiss reg = <0x00100000 0x1f4200>; 49*95ba6820SLuca Weiss clocks = <&rpmhcc RPMH_CXO_CLK>, 50*95ba6820SLuca Weiss <&sleep_clk>, 51*95ba6820SLuca Weiss <&pcie0_phy>, 52*95ba6820SLuca Weiss <&pcie1_phy>, 53*95ba6820SLuca Weiss <&ufs_mem_phy 0>, 54*95ba6820SLuca Weiss <&ufs_mem_phy 1>, 55*95ba6820SLuca Weiss <&ufs_mem_phy 2>, 56*95ba6820SLuca Weiss <&usb_1_qmpphy>; 57*95ba6820SLuca Weiss #clock-cells = <1>; 58*95ba6820SLuca Weiss #reset-cells = <1>; 59*95ba6820SLuca Weiss #power-domain-cells = <1>; 60*95ba6820SLuca Weiss }; 61*95ba6820SLuca Weiss 62*95ba6820SLuca Weiss... 63