xref: /linux/Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on Milos

maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on Milos.

  See also: include/dt-bindings/clock/qcom,milos-dispcc.h

properties:
  compatible:
    const: qcom,milos-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: Display's AHB clock
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Link clock from DP PHY0
      - description: VCO DIV clock from DP PHY0

required:
  - compatible
  - clocks
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,milos-gcc.h>
    #include <dt-bindings/phy/phy-qcom-qmp.h>
    clock-controller@af00000 {
        compatible = "qcom,milos-dispcc";
        reg = <0x0af00000 0x20000>;
        clocks = <&bi_tcxo_div2>,
                 <&sleep_clk>,
                 <&gcc GCC_DISP_AHB_CLK>,
                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
                 <&mdss_dsi0_phy 0>,
                 <&mdss_dsi0_phy 1>,
                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
    };

...